Accellera Approves UVM Standard

Accellera, the electronics industry organization focused on the creation and adoption of Electronic Design Automation (EDA) standards and Intellectual Property (IP) standards, approved version 1.0 of its Universal Verification Methodology (UVM) standard.

This standard, developed by Accellera’s Verification IP (VIP) Technical Subcommittee (TSC) is available as the Class Reference Manual, accompanied by an open-source SystemVerilog base class library implementation, and a User Guide. The UVM standard establishes a methodology to improve design and verification efficiency, verification data portability and tool, and VIP interoperability.

“UVM puts in place a single, open standard to advance verification productivity within design teams and across multi-company design and verification collaborative efforts,” said Shishpal Rawat, Accellera chair. “In addition to the Class Reference Manual, a User Guide and open-source reference implementation are available to accelerate industry adoption.”

“This is a significant accomplishment because the new features were complex and required considerable effort to build from a full list of requirements,” said Hillel Miller, co-chair, Accellera’s VIP TSC. “The committee reconciled the requirements list, agreed to a specification, implemented them and tested the results in an effort that coordinated hundreds of people across several continents.”

“This was more than just a standards effort, it was a major software development project in a committee environment involving 18 leading verification companies,” said Tom Alsop, co-chair, Accellera’s VIP TSC. “Every major feature requested by the verification community was
implemented, including two new features built by the committee – a command line interface and Resource Manager.”

UVM 1.0 leverages features from the baseline UVM 1.0 Early Adopter (EA) release, a direct derivative of the Open Verification Methodology (OVM). This allowed the Accellera VIP TSC to focus on adding features found in other common methodologies to satisfy the agreed functional requirements to shorten the standards development cycle.

UVM 1.0 fully qualifies the baseline features, corrects most of the known bugs and implements enhancement requests. Major new features include a Phasing mechanism, a Register Package (derived from Verification Methodology Manual (VMM) technology) and support for the Open SystemC Initiative’s (OSCI) Transaction Level Modeling-2.0 (TLM-2.0) standard to model component transaction connectivity and communication. The Resource Manager is an upgrade to the configuration mechanism that makes it more general and includes a standardized command line interface. Additional new features include callbacks, message catching and functionality in the objection mechanism to manage end of test.

The UVM Class Reference Manual is available for no cost at www.accellera.org.