Display SERDES IP Cuts Consumption by 0.7W

Integrated clocking and interface IP provider Analog Bits has unveiled an application specific Display SerDes (Serializer/Deserializer) IP that reduces area by up to 25 times, die-costs up to 25 percent and power consumption by 0.7W.

The Analog Bits Display SerDes is designed specifically for next generation flat panel displays, integrating a low power macro with a fine resolution, low jitter video clock to drive new video standards such as V-by-One HS.

Analog Bits has achieved these technology milestones by customizing the IP's analog macro to market specifications. The Display SerDes can now be successfully ported to 90nm 65nm and 40nm designs.

One of the key Display SerDes' features is its ability to maximize the V-by-One standard. V-by-One HS is a low power interface display chip standard from THine Electronics, Inc. that reduces power, lowers component costs and extends connection ranges. Major display manufacturers worldwide have adopted V-by-One HS. Analog Bits innovative programmable approach aligns with V-by-One and other video interface standards making it ideal for a wide variety of flat panel display applications.

"Our clocking and interconnect products have long held a reputation for high quality – especially in video," commented Mahesh Tirupattur, Executive VP of Analog Bits. "Integrating our new low-power, high-bandwidth SerDes has resulted in a compelling solution for this growing market."

Analog Bits