Zener Diode Protects FPGA Inputs

Although 5V-powered logic is still common in many applications, most FPGAs support interface levels of 3.3V and lower. When you connect an FPGA to higher voltage levels, the FPGA’s application notes commonly suggest that you use the PCI (Peripheral Component Interconnect)-bus clamp diodes in the FPGA’s I/O blocks with an external series-limiting resistor to prevent damage to the FPGA (Figure 1). The PCI clamp diode limits the voltage to a level that doesn’t harm the input, and the resistance value limits the current to a safe level that doesn’t harm the PCI clamp diode. This approach works well in designs with low-speed signals.


FIGURE 1

However, when you use this approach with a higher-rate signal, the effects of the parasitic RC filter distort the signal (Figure 2). The circuit from the FPGA’s application notes requires a change, which you can accomplish without redesigning the PCB (printed-circuit board). In this case, substituting a zener diode for the resistor shifts the signal level without causing excessive distortion (Figure 3). The zener diode works with the PCI clamp diode and the internal pulldown resistor to set the voltage level at the input pin.


FIGURE 2


FIGURE 3


To set the static level at the input pin, you must enable the FPGA’s internal pulldown resistor to prevent the PCI clamp diodes from being driven too hard when the input is continuously high. The current from the pulldown resistor is smaller than the rating current of the zener diode. Low-voltage zener diodes also have round “knees” in the avalanche IV (current-to-voltage) curve.

This curve results in a zener voltage that’s lower than the rated value, so you need to use a higher-voltage zener diode. The diode should also have a low capacitance. The CZRU52C3, a 3V zener diode from Comchip, works well, reducing the circuit’s voltage by 2V (Figure 4).


FIGURE 4

Some parasitic effects in the zener diode will create other distortion to the waveform. The parasitic capacitance of the diode causes the diode to initially look like a short to the signal edges from the 5V driver. The FPGA pin will see a high-voltage overshoot for approximately 10ns, quickly decaying to the rated level of the input pin. The RC time constant of the pin capacitance and the pulldown resistance result in a slower drop to the final value, which the zener diode and the pulldown resistance determine. Figure 5 shows a detailed view of the leading edge.


FIGURE 5