Flexible FEC Solution Innovates Software-defined Radios

imec and Target Compiler Technologies launched a C-programmable flexible FEC (forward error correction) solution fit for future cellular, connectivity and broadcasting standards. The “flex FEC” solution competes in area and throughput with dedicated fixed-function hardwired implementations, yet offers the flexibility to support multiple standards thanks to software programmability. The C-programmable flex FEC ASIP (application-specific instruction-set processor) template supports LDPC (low-density parity check), Turbo and Viterbi decoding. Imec designed and optimized the ASIP architecture and generated a matching software development kit, using IP Designer, Target’s tool-suite for ASIP design.

“To support the industry’s search for increased flexibility and reliability for their next-generation wireless devices, Imec’s green radio program aims at developing solutions for low-cost and low-power reconfigurable radios. Multistandard flex FEC decoders will become ever more important as enablers for future 4G networks. Therefore, we are pleased that Target’s IP Designer tool-suite enabled the design of our flexible C-programmable FEC processor template, offering competitive area and throughput numbers compared to dedicated fixed-function hardwired implementations, while offering full hardware reuse and flexible memory allocation,” said Liesbet Van der Perre, Green Radio Program Director at Imec.

Imec’s ASIP architecture template can be instantiated for different standards to perform channel decoding. Various algorithmic-architectural co-optimizations enabled parallelization of the algorithms to meet the high throughput and latency requirements in a flexible processor. The solution meets throughput and latency specifications ranging from connectivity (WLAN 802.11n, 802.11ac) to broadcasting (DVB-T2/S2, CMMB, DVB-SH) and cellular standards (3GPP-LTE, 802.16e).

Target Compiler Technologies’ IP Designer tool-suite enabled the design-time architectural exploration and optimization of Imec’s flex FEC solution and allowed a quick validation of the impact of architectural changes on throughput, latency, silicon area and power consumption. IP Designer automatically generated an optimizing C-compiler to compile the multi-standard FEC algorithms on the specialized FEC architecture exploiting the available instruction-level parallelism, and an instruction-set simulator to validate and profile the code running on the architecture.

The flex FEC template was instantiated for WLAN, WiMAX, 3GPP-LTE and DVB-S2/T2. A low-power register-transfer level hardware implementation of the core was automatically generated with the IP Designer tools, which resulted in a total core area and throughput competitive with state-of-the-art dedicated fixed-function hardwired solutions. The generic template, supporting both turbo and LDPC decoding can be pruned aggressively in case of LDPC decoding only, leading to substantial additional savings in area and power consumption.

Imec

Target Compiler Technologies