Synopsys Announces Reprogrammable NVM IP in 180nm Technology

Synopsys Inc. has announced the immediate availability of DesignWare AEON Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP products include few-time programmable (FTP), multiple-time programmable (MTP) radio-frequency identification (RFID) and erasable programmable read-only memory (EEPROM) IP solutions. Synopsys offers DesignWare AEON NVM IP for leading process technologies in more than 100 different memory configurations, all qualified to the appropriate industrial specifications.

Implemented in standard CMOS process technology with no additional mask or process steps required, the DesignWare AEON NVM IP is ideal for wireless, RFID and analog and mixed-signal SoC designs. Synopsys' broad portfolio of MTP and FTP NVM IP solutions delivers optimized electrical performance for a wide range of end applications, including: performance trim and calibration in precision analog designs, data storage in ultra-low power wireless applications, or high endurance in real-time datalogging applications. These solutions help designers reduce the cost and risk of integrating NVM IP into their SoC designs.

A key advantage of the DesignWare AEON embedded NVM IP is that no high voltage generation circuitry is required – all programming and re-programming is done using a standard CMOS technology with no additional masks or process adaption. This allows designs to operate from a single core supply, eliminating the complication of generating a separate, high-voltage signal for NVM programming, or supporting a high-voltage I/O pad. In addition, DesignWare AEON NVM IP provides support for extended temperature ranges beyond industry standard (up to 125°C for commercial and industrial products and up to 150°C for automotive products), which enables designers to develop robust SoCs that can withstand harsh process, voltage and temperature variations.

The DesignWare AEON products allow designers to choose the best configuration to optimize power, performance and area for their applications' SoCs:
• AEON/FTP Trim: ideal for analog and mixed-signal SoC designs, this solution provides area efficiency (256 bits in <0.07mm²) and offers up to 100 write cycles and additional flexibility over one-time programmable (OTP) solutions
• AEON/MTP RFID: targeting RFID and wireless SoC designs, this ultra-low power solution offers up to 1,000 write cycles, with read operation down to 1V
• AEON/MTP EEPROM: fully qualified to automotive grade standards (AEC-Q100), this product provides support for up to one million write cycles at high temperatures (up to 150°C)

Synopsys