Lattice Unveils PCIe 2.0-compliant FPGA

Lattice Semiconductor has launched its LatticeECP3 FPGA family that is compliant with the PCI Express 2.0 specification at 2.5Gbps. The LatticeECP3 FPGA and its PCI Express (PCIe) IP core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations at a recent PCI-SIG workshop, ensuring that Lattice’s solution is interoperable with existing PCIe 2.0 supported systems.

Achieving this significant industry milestone enables cost and power reduction with higher reliability for 2.5Gbps PCIe v2.0 systems for communications, multimedia, server and mobile platforms, and adds to the broad range of design solutions from Lattice and its IP partners that support the widely adopted serial interconnect standard.

The PCIe v2.0 specification allows operation at a lower speed (2.5Gbps), but the loop bandwidth characteristics are different and more rigorous than for PCIe v1.1. The Lattice solution allows customers who do not need the PCIe link to operate at 5Gbps, but who care about PCIe v2.0 compliance, to use a low cost FPGA in PCIe v2.0 compliant systems.

In addition, Lattice has worked with Trellisys Ltd to provide a robust and cost-effective PCIe Bus Functional Model (BFM) for Lattice's PCI Express x1 and x4 IP Cores. While there are a number of third party verification cores available for PCI Express, these are typically targeted at ASICs/custom logic and the cost of the verification IP often becomes prohibitive in the FPGA development flow. The Trellisys PCIe BFM concentrates on the transaction layer, since typically that is where the user application logic is implemented. This approach assumes that physical and data link layers, which are completely encapsulated in the Lattice PCIe IP cores, have already been verified by Lattice.

“The Trellisys PCI Express BFM brings the verification investment back in line with the FPGA development flow while still maintaining an effective verification concept,” said Charles Gardiner, Director, Trellisys. “Since PCI Express 2.0 has more rigorous testing requirements compared to PCI Express 1.1, successfully testing against the PCI Express 2.0 specification provides more robust operation with other PCI Express 2.0 compliant devices.”

The Trellisys PCIe BFM supports both Verilog and VHDL and has been verified on both the Aldec Active-HDL and Riviera-PRO simulators. It is delivered as precompiled code but provides the user with a powerful procedural library on which an advanced verification suite can be based. Designers can immediately begin the evaluation and design of PCI Express 2.0 compliant systems in LatticeECP3 FPGAs using the IPexpress tool within the Lattice Diamond 1.2, or later, design tool suite. The IPexpress tool provides the PCIe core, reference designs and all the scripts, BFM and simulation models needed to streamline integration into customer designs.

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