Xilinx ISE Design Suite 13.2 Brings Partial Reconfiguration to Kintex-7, Virtex-7 FPGAs

Xilinx Inc. has released the ISE Design Suite 13.2, providing support for the 28nm 7 Series families including the recently arrived Virtex-7 VX485T device being demonstrated to customers.

This latest edition of ISE Design Suite provides an up to 25 percent performance increase in designs targeting Virtex-7 2000T devices, the industry's largest density FPGAs built using Stacked Silicon Interconnect technology. The latest ISE software release also has enhancements to the PlanAhead design and analysis tool, providing partial reconfiguration support for Virtex-7 and Kintex-7 FPGAs, and front-to-back, integrated project management environment for improved productivity in designs targeting Spartan-6 FPGAs, Virtex-6 FPGAs, their defense grade counterparts, and all three 7 Series families including initial support for the low-cost Artix-7 family.

The award-winning ISE Design Suite provides designers the tools they need to facilitate global-team design, rapid feedback on key design considerations, best practices for low-power optimization using the XPower Estimator tool, and dynamic power reduction through intelligent clock-gating – all of which is accessible via the PlanAhead tool.

The PlanAhead tool has evolved from an I/O pin planner and floorplanner to a comprehensive development environment that accelerates time to production with unique integrated front-to-back environment that includes design analysis at each phase of the design cycle – RTL development, IP integration, verification, synthesis, place and route. The end result is rapid convergence on power consumption, resource utilization, and performance with fewer time-consuming design iterations.

"A key productivity advantage of PlanAhead is the tight integration of the design creation, analysis, planning and implementation features. With traditional FPGA flows, feedback on critical design parameters is only available late in the design flow," said Tom Feist, Senior Director of Software and Tools Marketing at Xilinx. "While runtime for synthesis and place and route continues to be a top focus for Xilinx, reducing the number of design iterations is just as important for accelerating development. Up front design analysis and design preservation flows that ensure timing from run to run are critical for our customers targeting our new 7 Series devices."

Enhancements to the PlanAhead tool include new clock domain interaction reports, tooltip language localization, and Simultaneous Switching Output (SSO) support for 7 Series flip chip BGA (FFG) packages. Updates to XPower Estimator (XPE) tool enables designers to make power-consumption predictions with a high-level of accuracy and see how Xilinx's choice of TSMC's high-k metal gate (HKMG) high performance low power process, and a unified FPGA architecture across families, deliver the lowest power of any FPGA in their class in most typical designs.

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