Samsung Tapes Out 20nm Test Chip on Synopsys Platform

Synopsys Inc.'s design enablement collaboration with Samsung Electronics Co. Ltd has achieved a critical milestone with the successful tapeout of the first 20nm test chip based on Samsung's High-k metal gate (HKMG) process technology. The test chip was implemented using Synopsys' Galaxy Implementation Platform, including the Design Compiler synthesis, IC Compiler place-and-route, In-Design physical verification with IC Validator, StarRC extraction and PrimeTime signoff tools.

The 20nm tapeout represents the outcome of early R&D collaboration between Samsung and Synopsys aimed at developing and validating a comprehensive design implementation infrastructure for the next generation of 20nm gigascale integrated circuits (ICs). Key 20nm design enablement innovations developed as part of the collaboration include modeling of new device structures, double-patterning-aware place-and-route and In-Design physical verification technology, and coding of advanced routing and design rule checking (DRC). Together, these innovations enable fast routing throughput while delivering full compliance with thousands of complex rules and manufacturable routing patterns.

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