Readying for 20nm

The industry is all set for 20nm tape-out. Last June Synopsis and STMicroelectronics announced that the R&D collaboration between them to develop an SoC design using ST 20nm process technology, co-developed with International Semiconductor Development Alliance (ISDA), has enabled ST to successfully tape out its first 20nm test chip. In February the Common Platform Alliance, a collaboration between IBM, Samsung, and GLOBALFOUNDRIES, revealed the details regarding the roll-out of 20nm process technology. TSMC is showcasing its 20nm Transparent Double Patterning design solution. At 20nm the pitch is beyond the lithographic capabilities of existing exposure systems and double patterning will become essential.

TRANSISTOR COUNT
I shall discuss two interesting observations arising from designs at 20nm. The Common Platform Alliance has disclosed that the number of transistor count will double yet again as designs go from 32/28nm, typically with 2 to 3 billion transistors, to 20nm. Does Moore’s Law continue to hold in spite of all-round predictions of its imminent demise? At this point, based on trends emerging from many semicon companies, I can only say that most of them are struggling to keep up with Moore’s Law, but the disclosure from the Alliance is an eye-opener that designers may have to reconsider the presumption that Moore’s Law has hit the wall. In the last few years Moore’s Law has shown a strange capacity of bouncing back from forecasts of its operational end. Sometime ago I had written in EDNAsia Comment that Moore’s law end was well supported by the latest tracked complexity metrics, such as die size, process node, clock speed, etc., based on announcements primarily from TSMC. I shall be glad if I am proved wrong.

The second observation pertains to the real estate on the silicon chip. The last two decades saw designers struggling to get more space on the silicon. Shrinking components and features on the silicon without destroying signal integrity or dangerously heating the chip was a challenge they faced successfully. But at 20nm the issue is abundance of silicon space that designers don’t know what to do. A consensus is emerging that extra components with no present use but possible future need should be built on the chip, which will be called superchip.

I see a parallel between this situation and that in the telecom industry a few decades ago when fiber optic cables were being laid. For long distance communications, telecom companies laid fiber cable much more than required. They saw a future need for it. These extra cables were called dark cables because they were not lit. Most dark cables continue to remain dark even today.

During the last four-five years, I have been seeing a trend to build extra capacities while designing chips. For instance, some chips have built-in complex power-saving facilities not used by consumers. Incorporating them into design is a waste of resources, both physical and intellectual. If such chips are produced in large numbers, they can cost a lot of money. Multi-core is another area where huge capacities are being built. Large amount of code is written to take advantage of multiple cores. But for most users some cores are usually powered down or completely off. In other words, “dark” hardware and software already exist in today’s designs, and designers need to tread carefully when thinking of 20nm superchip with its potential of providing more “dark” capacities.

PROBLEM WITH A DIFFERENCE
There is yet another angle to the issue of extra silicon. Call it a problem with a difference, because it is good to have this problem. The excess real estate provides the design process with more latitude. Even after the architectural stage, if need be components could be added on the chip without disturbing the built-up circuitry. Extra margins can be provided for. If problems are detected at a late stage, the designer has greater maneuverability to rectify them. Yet another advantage extra silicon offers pertains to proximity effects. When components are physically close, power, noise, and electromagnetic radiation from them affect the neighboring components, changing circuit characteristics, which can lead to irregular behavior. For instance, a noisy SerDes or I/O can distort an analog signal. Such problems can be better controlled at 20nm.