Droop-free S/H circuit possible in low-frequency apps

(Originally published in the January 23, 1986 issue of EDN )

An unacceptably large output error can result when a monolithic sample/hold circuit suffers a droop rate. This happens in low-frequency applications. This Design Idea eliminates droop error in the S/H circuit (Figure 1) operating two 8-bit multifunction converters back to back. A 5V supply is needed, and analog inputs between 0 and 2.5V are accepted although any input signal can be scaled and offset to fall within this range.



The analog input is applied to the inverting input of an LM324 op amp (IC1), which is wired as a comparator. The op amp and the IC2 multifunction converter form a ramp-and-compare ADC. (Because the Ferranti ZN435 multifunction converter includes a voltage-output DAC, an 8-bit up/down counter, a 2.5V bandgap reference, and a clock generator, you can configure the device either as an ADC or as a DAC.) The converter’s internal counter counts from 0, producing a positive-going ramp at the analog output.

When the ramp voltage exceeds the analog input, the comparator output goes high and sets IC5’s Q1 output high, thus inhibiting IC2’s clock and stopping the counter. IC2’s digital outputs are connected to the digital inputs of IC3, which is wired as a DAC. The DAC provides the S/H circuit’s analog output.

The output will remain in a hold state until you reset the monostable multivibrator (IC4), whose outputs apply simultaneous reset pulses to IC2 and IC5. The circuit then resamples and holds a new value of analog input. The S/H circuit provides 8-bit hold accuracy for analog input frequencies as high as 1kHz; you can use a faster op amp for IC1 for higher-frequency operation.