Circuit provides more accurate multiplication

Common analog multiplying devices employ methods using transistor parameters. Precise versions of these devices use the logarithm method of multiplication. This method involves the addition of logarithms and an exponential conversion (Reference 1). Using these methods, you can achieve a minimal error of ±0.1%. This Design Idea reduces the error, employs readily available standard components, and maintains the correct voltage scale.

The structure squares the sum and the difference of both components of the desired multiplication. The difference of these squared values yields the result of the multiplication. You can scale the desired multiplication of a and b using the identity of 4ab=(a+b)2− (a−b)2. In a conceptual diagram, blocks 1 and 2 represent the input part of the device (Figure 1).


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They comprise identical precise rectifiers. You implement these rectifiers with amplifiers A1, A2, A3, and A4 (Figure 2). They provide the addition and the subtraction of input voltages VA and VB. The rectifiers create the output voltages k(VA+VB), k(VA−VB), which have only positive polarity. You connect these outputs to a two-channel ADC, Block 3, and then to two identical DACs: DAC1 (Block 4) and DAC2 (Block 5).


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The ADC converts k(VA+VB) and k(VA−VB) to proportional codes N1 and N2. The ADC must handle the conversion over the full range of the absolute sum |k(VA+VB)|. The reference voltage of the ADC should be equal to the maximum expected value of |k(VA+VB)|. Codes N1 and N2 translate to Register 1 of DAC1 and Register 2 of DAC2, respectively (Reference 2). These codes establish the values on the R−2R dividers of each DAC. The output voltages of blocks 4 and 5, comprising N1|k(VA+VB)| and N2|k(VA−VB)|, pass through operational amplifier A7 in Block 6. You configure the op amp with a differential input, which takes the difference between the inputs and creates the multiplication result on the output. For example, if both voltages VA and VB have a range of ±10V and the input range of the ADC is 0 to 10V, then coefficient k=R2/R1=0.5. The full sum of each part should be ±10V. Table 1 provides the results for all four quadrants of these conditions.


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The systematic error of the multiplication is the sum of the discrete errors of the ADC and both DACs. This error depends on the resolutions of these devices. Choosing an ADC and DACs with greater resolutions will further reduce the overall error.


References
Tietze, Ulrich; Christoph Schenk; and Eberhard Gamm, Electronic Circuits, Second Edition, Springer, 2008, ISBN: 3540004297.

Peyton, AJ, and V Walsh, Analog Electronics with Op Amps: A Source Book of Practical Circuits, Cambridge University Press, July 31, 1993, ISBN: 052133604X.