Road to terabyte backplane mapped out

The long term future belongs to optical interconnects, low power processors and new kinds of memory architectures, said Prith Banerjee, director of HP Labs. Banerjee described the path to a terabyte/second optical bus as one step toward its vision of future systems architectures. Engineers need to embrace the new technologies to deal with the coming flood of digital data, he said. “By 2020 your end customer will be living in a world where people access 50 zettabytes of data from 30 billion mobile phones and 1.3 trillion sensors--and all that data will have to be analyzed by computer architectures you have to design,” he explained.

Long term, HP envisions exascale computers powered by vast arrays of smartphone-class processors. They will use board- and chip-level optical interconnects and huge pools of HP’s memristor non-volatile memories, according to Banerjee.

As a step in that direction, Banerjee described a 30GB optical backplane it created as a tech demo for its ProCruve 9200 switch. The backplane was built from a hollow metal waveguide bundling 12 10GB optical channels, costing as little as $10. “One of the keys was the use of MEMS to do phase reflectance of the light depending on the number of taps,” Banerjee said.

He sketched out multiple techniques including using more parallel lanes with more wavelengths to deliver a terabyte/second optical backplane. “You cannot do that with copper, and that’s the disruption,” he said.

Banerjee also discussed longer term projects in areas such as silicon photonics and free-space optics that hold the promise of chip-level interfaces and photonic processing. HP is likewise on track with partner Hynix to deliver the first commercial versions of its memristor components, which hold the promise of DRAM-like read/write performance in non-volatile storage.


This story was originally posted by EE Times.