Validation platform provides DDR4 bus, JEDEC timing analysis

LeCroy Corp. has announced a new validation platform that provides DDR4 bus and JEDEC timing analysis. Based on the company's first generation DDR3 analyzer, the new Kibra 480 platform features proprietary probing technology designed to non-intrusively monitor DDR4's higher transfer speeds without signal calibration and setup. The system analyzes bus traffic while identifying timing violations, and displays both commands and errors using a full function waveform viewer. With support for testing both DDR3 and DDR4, the system allows designers to speed memory integration and ensure design manufacturability.

DDR4 is the next evolution of the double data rate memory technology currently under development by the JEDEC standards organization. With operating frequencies from 800Mhz to 1600Mhz, DDR4 represents a significant advancement in performance with reduced power usage compared to DDR3 technology. Says Michael Romm, VP, product development at LeCroy Protocol Solutions Group "By incorporating our new custom silicon on a self-powered interposer probe, we're able to provide instant signal lock – including reliable capture of the DDR4 power-on sequence."

The Kibra 480 uses specialized trigger logic to automatically identify over 65 JEDEC timing and command violations across all ranks and banks simultaneously. This overcomes key limitations with logic analyzer-based solutions which use state-based triggering that is complicated to setup and can only track two or three violations simultaneously. In addition, the Kibra 480 highlights any errors in the timing display allowing users to see and verify interoperability and compliance to the DDR4 specification.

"The LeCroy Kibra 480 offers an economical way to increase test coverage and reduce time to market for DDR-based memory systems," stated Roy Chestnut, director, Peripherals Product Group at LeCroy. "Because the analyzer can be used for today's DDR3 and the next generation DDR4 standard by simply changing the interposer, memory verification teams can leverage the LeCroy solution across multiple design projects."

Upgraded software for the Kibra system provides several enhancements including a new Bank State View which allows users to visualize distribution of I/O operations across all banks. Additionally, the ability to capture Serial Presence Detect (SPD) data lets developers automatically discover the memory parameters used by system under test. The Kibra 480 is also fully compatible with DDR3. Customers can purchase the system with interposer probe sets for DDR3, DDR4 or both.

The LeCroy Kibra 480 will be made available in Q2 2012.


LeCroy Corp.