Implementation considerations of SDH clocks

Synchronization within transport systems refers to minimizing buffer slips to ensure a node both receives and transmits the same number of bits. In a digital network, common timing across every node ensures error-free transmission and switching. The quality (bit error rate performance), efficiency (slip rates, pointer adjustment counts), reliability (resistance to faults) and survivability (recovery ability) of a high-speed network depend heavily on its synchronization architecture and implementation.

Synchronization and distribution layer atomic functions
ITU-T G.781 provides atomic functions as part of the synchronization distribution layer and network synchronization layer of SDH. The synchronization distribution (SD) layer terminates and adapts the synchronization trails to the network synchronization and performs preselection of timing ports. The network synchronization layer selects the timing reference for the network element for synchronization distribution, and selects the reference for the station clock output. The performance characteristics of output clocks for the network element should follow the G.813 recommendation. Figure 1 is an example of a network element’s synchronization distribution layer functional model.

The station clock refers to the node clock or synchronization supply units (SSU), which distributes timing to synchronization equipment. The example also shows the SD accepting timing from line and tributary signals, both from SDH and PHD transports. Output B of the NC provides G.813 performance level of synchronization. Output A, also referred to as a SDH slave equipment clock (SEC), provides the station clock outputs meeting the jitter and wander requirements of G.813. Both outputs should be able to be selected independently of each other.



Implementation techniques of G.813 synchronization blocks
Transport systems partition system blocks into various functional blocks. The control cards perform management and control of the systems. Resource cards process switching and other data manipulations, while line cards receive and transport various payloads. The synchronization system can be implemented as distributed system blocks, a centralized timing system along with the control cards, and localized timing blocks for resource and line cards.

The timing architectture should map the atomic functions and interconnect a subset of functional blocks contained within the ITU-T recommendation G.781. The performance characteristics of output clocks for the network element should follow the G.813 recommendation. G.813 specifies Option 1 and Option 2 requirements for networks that support 2.048Mbps networks hierarchy and 1.544Mbps networks hierarchy respectively. A single synchronization system cannot act as both an Option 1 clock and Option 2 clock because of the mutually exclusive requirements within the two recommendations.

As illustrated in Figure 2, implementations split synchronization function into two functional blocks: the central timing and local line timing. The central timing function performs most of the standards requirements, such as selection of the best timing reference, jitter and wander filtering, reference switching, accurate holdover and so on. The central timing function supports redundancy with a master/slave configuration. The synchronization functions on the line cards select one of the back plane clocks and generate standards compliant highspeed clocks to drive the transceivers.



SDH equipment clock requirements
Timing cards generate a timing signal that is compliant to the synchronization standards. The basic phase locked-loop features, such as free-run accuracy, pull-in and lock ranges, are defined in the G.813 standard. Noise generation, tolerance and filtering requirements, along with the special features such as reference switching performance and holdover, are also included. There are additional requirements for clock output performances to input clock interruptions and other disturbances.

Noise is described as jitter and wander with respect to synchronization terminologies. The limitation for jitter generation at the optical transport output is in accordance with the optical line rates—the higher the rates, the more stringent the jitter requirements.

The jitter requirement is the only factor in the SDH transport system design that would change with the output optical rates. All of the other standards requirements remain the same, irrespective of the STM-N level that the system is designed for.

The output jitter specifications are mentioned for various bands of frequencies. In SDH systems, two jitter measurement bandwidths are specified: one for a wide-band measurement filter (f1 to f4 in Figure 3), and one for a high-band measurement filter (f3 to f4). The value f1 points to the narrowest timing cut-off frequency of an output timing signal that could be implemented by a PLL in a line system. Jitter at frequencies lower than this bandwidth pass through the system, while jitter at higher frequencies is partially absorbed.



The value f3 represents the bandwidth of the input timing acquisition circuitry. Jitter higher than this frequency will cause alignment jitter. Alignment jitter results in an optical power penalty: extra optical power is required to account for various degradations.

The value f4 reflects reasonable measurement limitations and is listed to establish minimum measurement bandwidth requirements and includes all expected, significant alignment jitter.

For the distributed timing architecture to be compliant with standards requirements and system level performance, the line card PLL bandwidth should be higher than the filtering requirement outlined by the standards. The timing card portion of the system should have the bandwidth suggested by the standards. The line card bandwidth can be tuned to have optimal bandwidth that would attenuate high frequency jitter in the specified spectrum. With a 20dB per decade attenuation with a second order implementation, to have a stop band starting at f1 (as in the standards) the 3dB cut-off frequency should be at f1/10Hz.

The jitter spectrum of the timing cards clocks becomes significant— the lower the phase noise of these clocks, the wider the bandwidths that the line card timing blocks can use. Noise tolerance is the range of input clock deviations the system synchronizer should accept while maintaining the required output clock and using the same input reference, and without generating alarms or going into holdover mode. The noise tolerance limits are defined considering worst-case network limits and various payload performances.

The noise transfer specifications are connected to the and width requirements of the EC. With the synchronization ha in structure in G.803, there could be SSU clocks and SEC clocks connected together. In order to avoid wander accumulation, it is recommended to have the SEC bandwidth at least 10 times that of the SSU. The G.812 clocks have a 0.1Hz bandwidth which points to the 1Hz minimum bandwidth limitation on the SEC clocks. The high bandwidth limit is derived from the jitter tolerance limit on the transceiver down the hierarchy.

The filter should smoothen the output phase hit to a tolerable limit for the lower hierarchy transceiver. G.825 SDH interface requirements describe the input jitter tolerance at STM-4 levels to have 7.5-ppm slope for 120ns. The 16ms time constant requirement (derived from the maximum defined phase slope error) and damping factor greater than three reflects a bandwidth of 10Hz. Combining both conditions, the requirement for loop bandwidth is between 1 and 10Hz for Option 1 networks. For Option 2 networks, the maximum loop bandwidth is 0.1Hz to filter out rapid transients on 1.544 M clocks based on G.824 hierarchy.

Special features on SDH Synchronizers
In the event of network error or disruption, holdover is a memory mechanism to synchronize output clocks using the last known defined “good” frequency accuracy. When the input reference becomes unavailable, holdover regenerates and outputs a last good sampled and stored frequency. A number of factors may reduce the accuracy of the clock in holdover mode, including the transition into the holdover, the initial frequency offset, variations due the clock going into holdover and aging.

Switching clock references may be required for a number of reasons, including physical clock losses, quality level degradation and timing loops. When the references are switched and the output clocks are synchronizing to new references, there should be limited output phase variations in terms of the amplitude and the slope. G.813 recommends reference switching though holdover state. The reference switching could last up to a maximum of 15 seconds, with two 120ns maximum phase errors with 7.5 ppm phase slope and the remainder with 0.05 ppm. The two 120ns relates to the input jitter tolerance of 240ns on G.825 with 7.5 ppm phase slope, allowed for entry into and exit from the holdover states.

There are input signal interruptions that may not cause a reference switch, including single clock pulse loss. There could be impairments because of internal testing and other disturbances. The special features also include implementing techniques to monitor input references for single clock failures as well as monitoring multiple clock cycles for impairments.

Conclusion
Understanding timing standards on high-speed transport networks are important while designing timing architectures for SDH-based systems. This paper provides an overview of the network standards and details the various requirements from the implementation perspective. The paper also describes various architectures and outlines implementation proposals for network synchronization on telecommunication networks, specifically on SDH.

Author information
The author holds B.Tech Degree from University of Calicut, India and M.Tech degree from Centre for Electronics Design and Technology, Indian Institute of Science (IISc), Bangalore, India. Technical interests include Network synchronization for high-speed networks and Voice over Packet technologies.