Dual-core chips: The shadow falls

Dual-core microprocessors have become a buzzword today. Both semiconductor and machine makers are lining up dual-core products. The last Computex at Taiwan, now the second biggest computer show in the world, after CeBit, showed major computer makers showcasing servers and PCs using dual-core chips. Intel’s Xeon, AMD’s Athlon and Opteron, and IBM’s and Freescale’s forthcoming ICs are among the core chips ushering the dual-core era.

What does the new era mean to the designer? Among the two greatest problems in deep submicron chip design are power consumption and heat. Some years ago, these issues were an afterthought; now they are fundamental to any design idea, from concept to implementation. While increasing the clock speed has been the traditional approach to increasing chip performance, the problem with this approach is heat. High clock speed means more heat, and for designers this means not only evolving better methods to dissipate heat but also coping with errors resulting from heat. The electrical radiation, or leakage, from one pathway to another in a chip corrupts data. In the extreme case, the chip may seize because of heat, or the program may crank because of errors.

Dual-core chips will ease the problems due to power consumption and heat. Adding a second core allows the chip to split computing tasks into smaller pieces, which not only enables the job to be done faster with reduced computing time but also with lesser power consumption and heat dissipation.

Designing of microprocessors is undergoing a change with the dawn of dual-core. Since the beginning of the microprocessor story, designers have followed a reliable pattern of shrinking the transistor size on a chip and increasing speed. This traditional method of improving performance is less effective at submicron nodes. The key performance measurement has been instructions per clock, which is the number of commands a chip can issue with every cycle of its internal clock. An important point sometimes missed out by designers is that a higher clock speed does not necessarily mean higher performance. The AMD processor pipeline is shorter than Intel processor pipeline, which is one of the reasons that AMD processor with lower clock speed can compete with higher clocked Intel processors. The best chips have a peak of three or four instructions per clock. However, even with the best designs, the average number of instructions per clock is much lower—as low as 1.3or 1.4 per clock. It is the flattening of the clock speed curve that designers are taking another route to be on the performance curve.

To what extent multiple-core processors hold the promise of improving performance beyond that of a single processor? Are Intel and AMD using dual-core more as a selling feature to demonstrate their R&D capabilities, or there is more to it? The advantage of dual-core to the designer is clear, but to the user is unclear. Unless you are a heavy user in need of complex operations, using dual-core would not give any distinct feeling of differences. Software not written to take advantage of multiple cores cannot bring the advantages of multiple cores to the user. Computers with dual processors need Symmetric Multiprocessing (SMP). SMP capability is something that is written into the code. The program must know that it can utilize two or more processors simultaneously. Most PC softwares are not SMP aware.

Intel has been using hyperthreading for some years. This technique allows a single-core chip to act on two instructions at once. Intel has asked partner companies to adapt their software for hyperthreading.

A point often overlooked is that a dual-core processor won’t be twice as fast as a single-core processor, but somewhere in the middle. Though there will be two pipelines and two caches, there will be one bus. An important design challenge is to ensure that the two cores will have to be designed in such a way that one “waits patiently” as long as the other is accessing the bus; if both access the bus simultaneously, a comedy of errors will result.