Using a SAR ADC for current measurement

In a typical motor-control system, as shown in Figure 1, the currents and voltage of the motor phase windings are measured and converted into a digital format for use by a microcontroller (µC) or digital signal processor (DSP). Due to the high voltages on the motor windings, electrically isolated Hall effect closed-loop sensors are used to convert the electric field from motor currents into a voltage within the input voltage range of an A/D converter. Multi-channel successive approximation register (SAR) A/D converters are used for simultaneous sampling to maintain correct phase information. This application report will analyze the application of closed-loop current transducers and how to achieve the best signal-to-noise performance from the A/D converter. In our example, the ADS7864, a 6-channel, 12-bit, 500kHz SAR-type A/D converter, will be used.



Analaysis of A/D converter input during sampling time

For the input stage of a SAR A/D converter, the equivalent circuit in Figure 2 can be used for analysis. Sampling capacitor CS has an initial charge of voltage V0 before switch SW is closed. This is left over from a prior conversion. During acquisition, input switch SW is closed. Sampling capacitor CS will be charged through source resistor RSRC and switch resistor RSW from the signal source, which during the acquisition period has output voltage E. Equivalent resistance RS is equal to the sum of signal source resistor RSRC and switch resistor RSW. Switch resistor RSW in the case of the ADS7864 is about 20.. A plot of Equation 1 describing the voltage on capacitor CS after switch SW is closed, is shown in Figure 3.



Our goal is to determine the acquisition time needed to charge the input capacitor to the value that is less than 1/2 LSB in error with respect to input signal. This is described in Equation 2:



The analog input signal to the ADS7864 (in single-ended mode) is ±VREF around VREF. In this case, the reference voltage is an internal reference of 2.5V, so the analog input signal is ±2.5V around 2.5V. The input signal range is from 0V to 5V. The difference between the most positive and most negative analog input of the converter’s operating range is full-scale range (FSR) and in this case is 5V. To analyze the worst case, input signal voltage E from the signal source will be equal to the full-scale voltage. The ideal code width of the 12-bit converter or 1LSB will be E/212. Replacing the value of 1LSB in Equation 2, it is possible to derive the value on which the input capacitor is supposed to be charged at the end of the acquisition time, as shown in Equation 3:



Substituting Equation 3 with Equation 1 and assuming that this condition is satisfied at the end of the acquisition time, we get the following result in Equation 4:



Now it is easy to calculate the required value for t..



The initial charge for different SAR converters is different and can be 0V, VREF, full-scale voltage, etc. The initial charge depends on the internal structure of the converter. In our case, the initial charge (V0) of sampling capacitor CS will be half of the FSR because the VMID is half of the supply voltage (or half of FSR) for VREF equal to 2.5V. The acquisition time must be a minimum of 8.32 times the time constant, when replacing V0 with E/2 in Equation 5 (above).

For a 12-bit A/D converter like the ADS7864, it is good practice that the acquisition time is 9 to 11 time constants. Knowing that internal sampling capacitor CS of this converter is 15pF, we can determine the maximum value of input resistor RS. The equivalent input resistance, RS, is equal to the sum of signal source resistor, RSRC, and switch resistor, RSW (Equation 6):



Verification of DC performance parameters

For this experiment, the DEMADS7864 evaluation board was used. First, one input pair of the A/D converter, positive and negative, is connected to the internal reference voltage of 2.5V. One pair is shown in Figure 4. Ideally, a Gausian probability density function (PDF) should describe a histogram of a large sample of conversion results. In this test, 8192 points were collected.



The Gausian PDF is defined by specification of a mean (µ) and variance (2). X is a digital output sample of the A/D converter and n is the number of samples.



The mean and variance are estimated from the sample set of data using the following equations:



The mean (µ) is the expected or average value. It is used to measure offset errors. The variance (2) describes the variability of the distribution about the mean. It isused as a measurement of uncertainty or noise.

The square root of the variance is called standard deviation (
), and it is a measure of the effective or root mean squared (RMS) noise. The peak-to-peak noise can be determined from the RMS noise value:



In measuring dynamic performance, two parameters can be calculated. The ideal SNR of the A/D converter, assuming the only noise source is quantization noise, can be calculated by the following equation:



The “noise floor” is set by the A/D converter’s resolution and the number of samples used in the FFT. The FFT is done using coherent sampling and without windowing.



For a 12-bit converter with full-scale voltage range of 5V (1.768VRMS), and 8192 samples we can calculate following:



When the noise is random, the FFT and histogram tests should correlate with each other.

The results just calculated represent our the best performances we can expect to achieve, as shown in Figures 5 and 6.

From the description of the closed-loop Hall sensor, this is a ± 5V output signal connected to A/D converter specified for ±2.5V around 2.5V input signal. The sensor manufacture specification prohibits using a measuring resistor of < 50., so this signal must be atteuated and level-shifted. The negative input is directly connected to internal reference voltage (see Figure 7). The positive input is connected to a proposed resistor network. Referring to Equation 6, resistors R1 and R2 are chosen to have 3k. values so that Thevinin equivalent resistance on the input to the A/D converter is 1.5k.. To verify this worked, the measurements were repeated with the inputs tied to ground.

Again, a histogram and FFT are done using 8192 points and the new results are presented in Figures 7 and 13.

RMS noise and average spot noise are calculated again:



The differences between the two sets of measurements show a change in offset and noise caused by the resistive divider on the input of the A/D converter. To balance source impedance and minimize offset, it is good practice to tie the negative input to VREF with a 1.5k resistor, at the expense of a slight increase in noise.







Verification of AC performance parameters
To verify AC performance, the same configuration is used. The signal source has ±5V output connected to resistor R2. This is replacing the Hall effect closed-loop current transducer with its measuring resistor on the output. The connection diagram is presented in Figure 10. To study the sensitivity of system performance with respect to the sampling, or acquisition time, a series of tests were run sweeping the acquisition time as a parameter. The input signal is approximately 15kHz and full-scale, and there were variations in system clocking frequency and sampling frequency. Results are summarized below. The measurements are done for different conditions and different acquisition times. In every measurement, 8192 points are sampled and FFT is calculated. Table I summarizes the data and present as a function of acquisition time. Data from Table I are presented in Figures 11, 12, and 13.

Conclusions
The results in Table I and Figures 11 to 13 show changes in AC performance as a function of acquisition time. The input resistor network was calculated based on the internal sampling capacitor of the A/D converter, which is 15pF, and an acquisition time of 250ns. By increasing the acquisition time from 250ns to 400ns, better performance is obtained without significantly reducing the sampling rate. If the master clock is running at full speed (8MHz), the conversion time is 1.625µs. By changing the acquisition time from 170ns to 420ns, the total conversion time will increase from 2µs to 2.25µs. Making the acquisition time longer allowed the signal-tonoise ratio to increase from 63.1dB to 71.5dB and at the same time, THD will decrease from –58dB to –78.6dB.

Authors' Information
Miroslav Oljaca has over 17 years of design and managment experience in the field of motor control and power conversion. He currently specifies and supports products that provide motor control solutions targeted at high-precision motor control applications. He can be reached at oljaca_miroslav@ti.com.

Justin McEldowney has been designing analog ICs for Burr-Brown, and now Texas Instruments, since receiving his BSEE from the University of Arizona in 1984. Prior to this he developed a motor controller as a co-op student for Inland Motor Co. Currently, he manages a design group developing A/D converters. He can be reached at mceldowney_justin@ti.com.