"Magnitude of the problems favors consolidation"

EDN Asia: How far is it true that the present generation of EDA tools is meant for 130 and 180nm, and not 90 and 65nm nodes?

Camposano: EDA, and certainly Synopsys, is ready for 90 and 65nm. While there is a lot to address, we are working on the issues and have them under control. There are many similar, basic steps in the design flows for 90 and 65nm. While many capabilities need to be enhanced for both 90 and 65nm, a 100 percent radical change is not required. The most significant changes will be in handling power. For example, issues of multiple supply voltages, dynamic voltage and frequency scaling, and multi-threshold voltages are currently being worked out for both dynamic and leakage power. Timing analysis will also need additional capabilities, in particular dealing with parasitics and chip inductance for very fast signals. Statistical timing analysis is a major issue at 65nm in particular. Rather than doing worst-case analysis on timing, design engineers need to do statistical analysis on delays. Finally, EDA flows have to deliver additional physical design capabilities, more aggressive mask synthesis, like strong PSM for many mask layers, and better, more unified verification to address the complexity of the smaller geometries.

EDN Asia: In which nodes will most designs be done during the next five years-180, 130, 90 or 65nm?

Camposano: Most designs are currently being done in 130nm. This transition has just happened. While Synopsys is seeing advanced designs at 90nm today, we expect the mainstream transition to 90nm, and then to 65nm, each to take two years-maybe a little less. It is critical that EDA companies work on addressing the challenges related to these smaller geometries now. This is a key reason Synopsys is beginning to work on design for manufacture (DFM), for example.

EDN Asia: Is there an increasing gap between the actually available EDA tools and the number of gates?

Camposano: We don't currently see the design gap increasing. As a matter of fact, there are some key things happening to master complexity. These include increased use of intellectual property (IP) that has good reusability, and advanced verification technology such as SystemVerilog, including assertions and formal techniques.

EDN Asia: What are the main challenges facing the EDA industry today?

Camposano: The key challenges facing the EDA industry today include power, statistical timing analysis, more advanced physical design capabilities, mask synthesis, design for manufacturability and advanced verification.

EDN Asia: Do you envisage EDA companies coming together to collectively face these challenges?

Camposano: In general, EDA companies are aiming to design open platforms to enable collaboration and make sure tools can work together. However, the magnitude of the problems favors consolidation. We have seen this trend in both the semiconductor and EDA industries-customers are looking for a single, trusted provider to mitigate their risk.

EDN Asia: Will the EDA industry move ahead along traditional lines, or will the industry have to build a totally new category of tools for deep submicron?

Camposano: It's a mix of both. While a lot of things will continue to be done the way they are being done today, new categories such as DFM tools are necessary to address the convergence of design and manufacturing and move us further into the silicon infrastructure arena. Remember that the EDA industry lives in constant change. A higher level of integration of tools into platforms and solutions is becoming increasingly attractive to customers. And when we talk about integration, we are talking about true technical integration, not about marketing platforms and sales packages.

EDN Asia: It is often said that the economics and technologies of deep submicron are at loggerheads. Any comment?

Camposano: As we move to smaller technology nodes, a greater capital investment in fabs is necessary. The non-recurring expenditure of design, including masks and tools, also go up. This implies a need for higher volumes to recover investments. Consequently, chips are becoming more complex in order to address a bigger application space. This is not a new trend; it's been going on for a long time. We don't see any fundamental economic limit in the next few years.

EDN Asia: How is the EDA industry geared for new technologies like silicon-on-insulator or SiGe bicmos?

Camposano: From the EDA viewpoint, there is nothing fundamentally different in approaching these new technologies and we believe we are well geared for this. If we model things correctly, we can, to a large extent, handle technologies such as silicon-on-insulator or SiGe bicmos with existing tools. To do this, we need to consider the appropriate models. For example, Spice would need specific electrical models.

EDN Asia: With the amount of software-on-a-chip exploding, how is the EDA industry affected?

Camposano: From the design viewpoint, the exploding amount of software-on-a-chip points towards more complex platforms around IP such as processor cores and DSPs. Additionally, system-level tools used to design the software on chips need to leverage efforts such as SystemC.

EDN Asia: Would you comment on the relative importance of ASICS, ASSPs and FPGAs in the next three or four years?

Camposano: ASICs, ASSPs, FPGAs and newer approaches such as structured ASICs all have their places in the semiconductor ecosystem. From an EDA viewpoint, ASICs and ASSPs are designed in a similar way. As non-recurrent engineering costs become higher, FPGAs become more attractive for lower volumes. This is a trend that will increase. However, as FPGAs get more complex, their design methodology gets closer to an ASIC design methodology. Because of this, we expect FPGA users to invest more in advanced tools.

EDN Asia: Is Synopsys working on any pioneering technology nowadays?

Camposano: Synopsys is always working on many pioneering technologies. For example, we are already addressing the key challenges mentioned earlier-power, statistical timing analysis, more advanced physical design capabilities, mask synthesis, DFM and advanced verification. Some of Synopsys' most significant technology investments are in DFM and mask synthesis, and we are a driving force behind SystemVerilog, assertions and constraints in verification.

You can reach Kirtimaya Varma at kirti.varma@rbi-asia.com