New issues in implementing IPs

When ARM Ltd bought Artisan Components Inc. last year for $913 million, there were doubts expressed about the logic behind the deal. ARM and Artisan were two companies with widely different technologies and distribution channels. ARM’s forte has been in meeting the needs of architectural designers through providing them MPU cores to differentiate their designs, while Artisan’s has been in understanding the physical layer through building libraries ensuring RTL correlates well to silicon. Both the companies were struggling in a fiercely competitive declining market. Some analysts said that the deal was an attempt to become big through acquisition when through growth was not possible. However, executives from both the companies said that the deal was a strategic acquisition, allowing ARM to ensure that its MPU cores and other cores to be more closely correlated with actual silicon, with ARM cores built with Artisan libraries.

This is just one example of how IP is becoming a jigsaw puzzle in which integrating tools and processes are becoming critical. For one thing, only a handful of IP companies have been profitable. And now it is increasingly realized that a company designing a full chip cannot make profits. With every company working to increase productivity and to decrease cost, risk and time-to-market, IP is emerging with a key role in achieving a company’s goal. However, IP cannot provide the best competitive edge if considered in isolation. Implementing IP solutions should tie up together with verification and DFM, and also tie up with foundries at 90nm and deeper. How IP gets implemented or verified would determine the fabric, whether it is SoCs, ASICs, structured ASICs or FPGAs.

Building a methodology for integration and knowing the tools to support the integration is emerging a very specialised job

When a designer decides which IP to get, the list of his criteria for getting the appropriate IP is now much bigger than what it used to be some years ago. While he starts with dependability of supplier to provide and support, quality, tapeout, etc., he has to bear in mind the need to acquire more IPs from different sources and their all tying up together through various processes from design through production. How the IP works in isolation and how it works when integrated into a system are now two sides of the same coin. An additional care for the designer is to convince himself that each of his IP supplier is stable enough to survive for the next few years when his company will offer products based on the IP.


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It is no more just building the IP or getting the IP; building a methodology for integration and knowing the tools to support the integration is emerging a very specialized job. This situation is leading some to believe that companies may in due course be headed for a Chief IP Officer, who will maintain strategic relationships with a horde of vendors.

An emerging situation is that companies in competition will need to cooperate with one another. Each IP company has its core strengths. For instance, ARM is strong in star IP and processor IP. Synopsys is strong in standards-based and interfaceconnectivity IP. A product may use Ips from ARM and Synopsys. For the success of IPs on the product, both the companies may need to coordinate.

Designers often question whether to make IP or buy it. It was believed that through making IP one can differentiate a product. Designers are veering round to the viewpoint that making all the required IPs is like re-inventing the wheel, and companies should spend resources in core competency to differentiate the product rather than in duplicating efforts. Companies have found better ROI on their silicon investment by extensively using third-party IPs.

By the time designs move to 65nm, IP developers will face many new issues. Subwavelength lithography will account for many of design constraints on cells, and the way cells are packed and interconnected. Issues such as pattern sensitivities, spacing rules and area rules will be applied across the boundaries of IP blocks. In other words, IP implementation will become even more challenging.