Choosing the right “stacked” memory-packaging architecture for today’s microelectronics applications

In each new memory-packaging architecture, system designers must weigh the attributes of stacked die versus stacked chip scale packages and other manufacturing issues.

Increasingly, memory chips—in combinations of all their f lavors (i.e., DRAM, SRAM, Flash, etc.)—are at the forefront of microelectronics endproduct functionality. This is true for cellphone handsets, broadband devices, networking components, automotive modules, industrial tools, and computers. If the packaging mix of memory ICs with other memory ICs and/or other chips (i.e., logic, baseband, JAVA accelerators, CMOS image sensors, etc.) was simply a matter of getting smaller, thinner dies stacked into one package, memory architecture design would be straightforward. If every reduction in die or package size resulted in improved chip and system function and lower production cost, every application would follow the same packaging route. However, the complexities of mixing memory types and other chips into a given architecture for today’s consumer microelectronics is not that simple.

Each new application of memory in a microelectronics product requires detailed attention and careful analysis of the endproduct form factor, memory-die function, IC production yield, final testing, and more. Foremost to our discussion here, in every new memory-packaging architecture system designers must carefully weigh the attributes of stacked die versus stacked chip scale packages and associated manufacturing issues, such as wafer level packaging and using known good die (KGD). Packaging considerations must even consider production steps in the backend of wafer processing; thinner die packages smaller, but thinning some types of memory die creates memory functional problems, such as refresh time increases or single data-bit failures. All these issues tend to drive costs in different directions; at each step in any analysis, the impact on end-product manufacturing cost is crucially important.

In the discussion below,we focus on memory packaging considerations that systems designer must address for cellphone handsets. Most of these issues, however, apply across the spectrum of feature-rich consumer products being offered today because these products are all being driven by a common set of consumer demands. For example, the functions of wireless handsets and personal digital assistants (PDAs) are converging to similar underlying memory requirements. Handsets have gone from low-end voice only function to full video streaming, audio, camera functions and an open operating system architecture. The current leading edge wireless technology standards (e.g., 2.5G and 3G) have enabled faster data rates across an air interface, thereby enabling a new set of application programs to include MP3 players, multimedia messaging (i.e., text and JPEGs), sophisticated calendar organizers and high-speed video streaming on handsets. Most if not all of these functions are also being folded into PDAs where users, for example, can connect to the Internet to get a stock quote right at their finger tips.

A distinctive combination of memory chips to support high data performance, low power consumption, low cost, and high volume production to meet the consumer’s needs is not always easily achieved.

Handset memory considerations

As illustrated in Figure 1, the baseband and application-processor sections on a 2.5G phone each requires some form of memory— Flash, SRAM, PSRAM and/or DRAM. A system designer must decide what memory is best after considering performance, printed circuit board (PCB) space, device availability, price and so on.




As illustrated in the application processor section, even though mobile SDRAM is shown in the same functional block with other memory, in reality SDRAM needs to reside on a separate data bus because of interface differences. Including MP-3 music functionality consumes a good deal of memory; in this case, perhaps, removable NAND Flash would be a likely memory candidate.

With such new features, it is obvious that conventional memory architectures, such as a discrete low-power Flash memory chip and a discrete low-powered SRAM chip, are simply not adequate for newer wireless handset designs. First, the PCB area is space limited. Second, memory density is not adequate to support all the possible phone functions, as outlined earlier. Lowpowered SRAM is being supplanted with PSRAM as the one-transistor (1T) cell architecture is replaced by 6T architecture.

With memory densities e16Mb, handset designers are migrating to PSRAMs because die size is considerably smaller for the same memory density (e.g., PSRAM versus SRAM). Like the SRAM, PSRAM has a similar interface as Flash memory; this makes a “very friendly” companionship between Flash and PSRAM in stacked chip scale packaging (S-CSP) applications. However, it is important to review SRAM and PSRAM data sheets to determine if there is a drop in compatibility resulting from timing or signal changes in the system software. The data presented in Table 1 will help a handset designer determine what the fundamental differences are between a DRAM, PSRAM, low power SRAM and Flash memory devices.




Stacking mobile DRAM and Flash die is also a viable option, however, not necessarily as straightforward due to interface differences between DRAM and PSRAM. In addition, PSRAM standby current is generally lower than DRAM, which limits battery life in hand-held products where DRAM is used. Determining the best solution involving PSRAM and/or DRAM and the best interface for their application involves a designer reviewing bus-burst frequency requirements (i.e., whether the read and write modes are asynchronous or synchronous), active and standby currents, data organization (i.e., x16, x32, etc.) and PCB board layout.

For example, designing a PCB for PSRAM and Flash might be easier than using SDRAM because the latter requires additional interfacing. In addition, the JEDEC definition of word size for SDRAM is 512 words/page versus 64 words/page for a PSRAM. This alone can potentially reduce overall power consumption by ~70% using a 16-word burst.

Empirically, given the limitations and tradeoffs discussed above, stacked memory solutions are increasingly being selected rather than using a single memory die. For handset and other applications, the design community is moving rapidly to stacked memory using S-CSP and stacked packages.

Stacking die

When applying S-SCP, initially, a system designer must ensure that the space on the PCB allotted for the memory takes into consideration the z-axis specification driven by the number of die stacked vertically. Beyond this somewhat obvious issue, it is with stacking die where systems designers must extend their design considerations back into the final stages of chip fabrication (i.e., wafer processing). Ever thinner, ever higher memory die stacking does have some limitations; stacking die brings with it a new set of challenges, including wafer thinning, die testing, delamination and noise immunity between devices. One of the principle concerns is that contamination from wafer thinning can potentially end up in the depletion area (Figure 2) creating a charge loss from the storage cell into the depletion area ultimately increasing the refresh interval (tREF).




Increasingly, we are hearing system designers ask about the effects of wafer thinning on Flash, PSRAM and DRAM die. Memory suppliers are telling designers who are specifying sub-1.6mm or even 1.4mm S-CSP to be cognizant of the potential for wafer thinning to precipitate problems with single-bit failures, variable retention time (VRT), reverse tunneling affects, punch through and tREF; at times, these can be more pervasive than one would expect.

System designers need to get as much data as possible from memory suppliers about the minimum thickness that a memory die family can tolerate to guarantee performance and prevention of single bit failure. For example, designers need to ask: When DRAM wafers are thinned for use in SCSPs, at what wafer thickness can we expect to see degradation of the average tREF of the device?

Designers can rely on this type of information from memory suppliers as most are continually working on best known methods with respect to potential data retention issues. Experiments conducted in assembly houses in conjunction with memory suppliers have identify various potential causes of this type of degradation, but, to date, the exact cause or mechanism has not been identified. In fact, several factors seem to contribute including final wafer thickness in some cases, whether or not a chemical mechanical planarization (CMP) polish was performed after mechanical backgrind, the constituents in the water used during CMP, the make up of the CMP slurry and even thermal cycles after wafer processing.


<%@ LANGUAGE="VBSCRIPT" %>
<% Randomize: ord=int(rnd*1000000000) %>




While there is still no true understanding of the mechanism of tREF degradation in thinned memory chips, there are proven methods that can effectively eliminate these factors and that have improved the device yield. For example, if a CMP polish is required after backgrind, it is absolutely critical to use the proper slurry and water. Better yet, the best solution may be to not use slurry at all, but to simply improve the wafer surface via a mechanical polish at the completion of backgrind—with key considerations of wafer stress and die cracking if the backside is not planar.

Studies have shown that mobile ion contamination on wafer surfaces can cause transistor degradation when the depletion area in transistor wells becomes contaminated. It has been widely quoted that the metal contamination tolerance level for a 16MB DRAM, is on the order of 1010 metal atom/cm2. Metal surface contamination particularly deposited from aqueous HF, has also been thoroughly investigated. In addition, anions, such as Cl-, may produce charge species that are mobile in electric fields and, with elevated chip operating temperatures, can cause unpredictable conditions, such as device drift or any other instability, possibly tREF.

Considering the referenced affects on the wafer surfaces, perhaps with <6 mil wafers and elevated diffusivity rates from insitu thermal cycles, trace elements are entering the wafer from the backside causing poor electrical performance. Figure 3 illustrates the cross section of a typical Flash memory cell; the first cross section shows normal operation, the second device punch through where, basically, the source and drain are electrically shorting subsurface rather than below the gate oxide or channel region. This can occur when there is a small amount of bias voltage applied to the device’s control gate when the p- substrate bulk sheet resistance has been contaminated.




As thinned memory die areas increase, there are packaging and assembling issues that can contribute to problems. For example, as the die area increases, applying a thinned die to another thinned die or to a substrate can stress the die to a point of cracking. Experiments have shown that there is a level of backside roughness from backgrinding that can propagate die cracking or die delamination, which both affect moisture sensitivity level (MSL). In addition, larger thinned memory die increase the potential for die adhesion materials precipitating stress during the material’s cure cycle; this can affect bond wire loops.

Even die test is impacted with a new set of challenges: When stacking two die the cost and yield impacts are minimal; however, stacking three or more die in a single package could lead to higher yield loss and increased costs to the end user. Using known good die (KGD) or, in some cases, good enough die (GED) does mitigate these risks and provides a reasonable confidence level that testing conducted at wafer probe reduces the amount of yield loss at post-assembly test. Plus, testing post assembly with the higher level of KGD reduces the test suite to open, short and continuity testing only.

Stacking three or more die in a single package could lead to higher yield loss and increased costs

Memory IC manufacturers offer different levels of KGD: DC only or DC and AC functionality. Adding AC est functionality at the wafer level is very costly, but for multiple die stacking it is has some decided advantages; expect to pay more for memory with this level of testing. Today, there are few suppliers that offer this service. It is best to understand what level the supplier will guarantee prior to committing to high volume production. Overall, when stacking die, the risks include delamination from surface contamination precipitated in wafer processing, die stress (bowing), injection molding damage or subsequent thermal cycles in the assembly process. There is also the possibility of die thermal affects caused by stacking. For example, with a memory stacked on a baseband chip to save space, perhaps DRAM tREF might increase because the stack traps more heat. Unless this is situation is modeled correctly, it could reduce battery life.

Package stacking

Package-on-package stacking is gaining traction in the industry as an alternative to die stacking. With package stacking, any yield hit is taken at the single or dual-die package level before they are integrated using standard surface mount technology (SMT) techniques. Stacking packages allows integration of the same type or size die and stacking digital baseband with memory or memory with an application processor. One principle advantage is that this allows for multiple sourcing of memory devices and a reduction in costs to the end user. This also helps testability when the testing of memory and logic is done separately before package stacking. Testing memory and logic together is not trivial as you need mixed signal testers and/or separate test f lows.From the handset point of view, z-axis limitations are, perhaps, the biggest disadvantage to package-in-package integration of memories or memory and logic. The z-axis in the more advanced handsets is often very limited; this could mean that the only adequate solution is die-on-die stacking. Figure 4 shows an example of a die-on-die stack as well as packageon- package stacking.




Battery power considerations

With the demands of the latest generation cellphones, power consumption and standby current are an important consideration for system designers. Designers need to adequately evaluate having adequate power supply loading for active read-and-write modes and total current, but also factor in standby time when the handset is not in use. Standby time, when a handset is in its battery charger rather then in the hand of its user, could be a significant amount of time. Balancing the tradeoffs could mean using higher performing memory that may need higher active and standby currents, but would require significantly less time to download a JAVA applet compared to a previous generation handset.

Comparing needed total current consumption with a given battery supporting higher performance memory versus lower performance can determine what the best solution is for any given application. Other considerations could be to use a synchronous device instead of an asynchronous device, if the digital baseband (DBB) supports this feature, given that that the synchronous device can yield higher data throughput versus an asynchronous device albeit the active current may be higher.

Cost versus benefits

Overall, when reviewing the various memory options available on the market today, designers need to understand how to determine what is best for their particular application. They must take into consideration data throughput, battery life, execute in place versus code shadowing, PCB area savings, and packaging either die stacking, system in a package or package on package. Each of these options has it advantages and disadvantages. For example, package-on-package offers a standard socket whereas a baseband could support DRAM from any manufacturer. Die stacking minimizes the PCB area taken in the application. Of course these options don’t come for free, as the final yield for each will be different due to the complexity of the components that would reside in these packages. Selecting memory that is more "commodity" type allows for price competition due to the abundance of supply, in contrast to a niche product which, by definition, would be more costly due to the availability of the devices.

Author information

Michael Steidl is Senior Vice President,Advanced Product Development for Amkor Technology.