TI announces "world's first" DDR-II PLL supporting 800MB/s for registered memory modules
( 01 Nov 2003 )
Texas Instruments Incorporated has launched what it claims as the world's first Double Data Rate-II (DDR-II) Phase Locked Loop (PLL) for registered memory modules that support data rates up to 800MB/s.
Said to support "the industry's highest frequency,"the high-performance, low-skew, low-jitter, zero-delay buffer gives designers wider timing margins necessary in designing high speed DDR memory modules found in applications such as PCs, servers, workstations and communications.
The CDCU877 DDR-II PLL is fully compliant with the JEDEC DDR-II standard and distributes a differential-clock input pair to 10 differential pairs of clock outputs and one differential pair feedback-clock output differential pair.
Combined with the SN74SSTU32864 DDR-II logic register, this device provides a total chipset solution and facilitates easier part sourcing for DDR-II memory modules. The SN74SSTU32864 can be configured as a 25-bit 1:1 pinout configuration or a 14-bit 1:2 pinout, allowing users to work with a single part number for multiple DIMM configurations.
The CDCU877 comes in a 52-ball MicroStar Junior BGA and 40-pin MLF package and is priced at $3.50 (1000).
