IP vs EDA

Last month we discussed in this column how IP implementation was becoming more complex for designers. Here we discuss some more IP-related issues.

What is now the key factor in design economies: IPs or EDA tools? The 2003 ITRS roadmap says that 75 percent of design productivity improvement will come from IP reuse and merely 25 percent from improved EDA tools, flow, or methodologies. The design industry has often criticized the EDA industry for not coming out with appropriate tools fast enough to bridge the ¡°design gap¡±—the gap between the advancing ability of chip makers to squeeze transistors onto a chip and the slow improvements in the availability of tools to designers to design circuits using these transistors. As chip design advances to 90 and 65nm and beyond, the ¡°design gap¡± is growing, and there does not seem to be adequate thrust in the EDA industry to bridge the gap. Not surprisingly the EDA turnover has been stagnating around $4 billion per year in spite of the great strides the semiconductor industry has taken in recent years.
It has been estimated from using market forecasts for ASIC and ASSP design starts and the ITRS projections of increased IP block reuse that there will be need of 100 billion gates of reused logic blocks in 2007 design starts. Which means 10,000 blocks of million-gate size, reused logic blocks. Which also means less use of EDA.

I think it is not tool limitation alone that is adversely affecting EDA. Even if EDA tools were to evolve to bridge the ¡°design gap,¡± designers may find reusing proven parts of previous chips faster than starting a design from scratch each time. With the constraints on time to market acquiring greater criticality for survival in business, design starts from the scratch are less capable of meeting market needs than IP-centric designs.

Another factor aiding IPs against EDA is the increasing shift towards standards-based systems. When designing such systems, the designer needs to meet industry standards, say MPEG-2 for video, and there is hardly any need to differentiate a system on the basis of functionalities. In such situations the need to design from scratch using EDA tools does not provide adequate gains. Not surprisingly, system companies are moving away from an internal chip design approach and are willing to source non-differentiated features through procuring IPs from outside sources.

However, stitching together large IP blocks is not the panacea it was hoped for. An industry consortium, Spirit (Structure for Packaging, Integrating and Reusing IP within Tool-flows), was formed two years ago to address issues pertaining to reusing IPs.

A long-term IP trend seems to be a shift from hardware implementation of core functions to software. Some years ago dedicated hardware performed MPEG-2 video decoding. Later, IP blocks were offered to perform the same function in a system-level chip. Now, some companies offer a range of video decoders and encoders supporting various standards in hardware or as software running on embedded processors. Embedded processorperformance is rising rapidly, with its power consumption and demand from silicon resources falling. More IP will migrate to software, bringing greater flexibility in responding to shifting standards, and providing vendors with the capability of making chips even before standards are finalized. This capability is a grea advantage in a market where timely introduction of a product means a lot to its success or failure.

It remains to be seen whether the move towards IP will change the fortune of IP companies. There are an estimated 150 IP companies, of which seven dominate, contributing almost 70 percent of the total IP revenue of $1.2 billion. Most IP companies have unsustainable financial resources. But the growing profile of IP might make the difference.

You can reach Kirtimaya Varma at
kirti.varma@rbi-asia.com