Tokyo Electron Limited (TEL) and Teseda Corporation have produced an integrated system which enables low cost of ownership (COO) by using design for testability (DFT). With increasing integration and funct ional ity of system-on-chip (SoC) devices, the cost and time for testing and test development are major obstacles. High-quality tests have made it impossible for testing to be performed manually yet still meet with deadlines. To overcome these difficulties, automated test generation techniques based on DFT methodologies have entered the mainstream . However, test systems specializing in DFT for wafer testing have not been available until now. The demonstration system cons is ts of the Wafer Prober P-8XL from TEL, and the Validator 500 from Teseda. The combined system enables wafer tests on semiconductor chips equipped with DFT circuits, making it possible to reduce both test costs and test design time.
