CDR chip for 3.125Gbps applications consumes only 108mW
( 01 Jul 2003 )
- By Terry Koh in Singapore
With high-speed communications demanding high power and, hence, requiring high heat dissipation, Sires Labs has introduced a 3.125Gbps clock and data recovery (CDR) chip that it claims has the industryÔs lowest power consumption of 108mW.
Aimed at optical communications, networking systems and transceivers, the SRL-3201 is a monolithic, integrated clock and CDR chip capable of extracting clockinformation from a SONET OC-48 or SDH STM-16 data stream with FEC overheads.
The SRL-3201 contains all the necessary functions to reliably lock on to an incoming NRZ data stream of 3.125Gbps. Its dual loop architecture has a wide lock range and stays firmly in lock with acquisition times of less than 50µ. For easy integration with other devices, NRZ data input, and clock and data outputs are compatible with LVDS levels. The CDR meets all ITU-T jitter requirements when used with recommended loop filter parameters.
The SRL-3201 requires minimal external components. Aside from the usual power supply bypass capacitors, it only requires LVDS bias resistors and a C-R combination for the loop filter. The low power consumption is attributed to its self-adapting bias (SAB) design, Sires Labs patent-pending technique, which also adapts to semiconductor process variations. This results in products with more uniform characteristics. It also increases wafer yield, hence lowering the cost of the chip.
The CDR is powered from a single 1.8V supply. It is designed using current-mode logic and is fabricated in 0.18µm CMOS. It is also available in IP form. Evaluation kits will be available in Q3 2003.
With high-speed communications demanding high power and, hence, requiring high heat dissipation, Sires Labs has introduced a 3.125Gbps clock and data recovery (CDR) chip that it claims has the industryÔs lowest power consumption of 108mW.
