Nanometer technolgy raises silicon integrity issues

Signal integrity issues such as crosstalk noise, crosstalk delay, power supply voltage drop, electromigration, wire self-heating, hot carrier injection and substrate noise, affect both functionality and the performance of designs. Unless they are detected and resolved prior to tape out, the consequences can be costly.

Nanometer designs aiming to satisfy low power, high device counts and high clock speed, can no longer be guard-banded to avoid signal integrity related problems. Communication and computer products require greater levels of functional integration on a single chip, as well as high clock rates. The increased device and interconnect density results in strong signal interaction through coupled parasitic capacitance between the interconnect wires and higher current density in the power network due to the switching currents in the devices. Both these causes have undesirable effects on the chip's behavior and performance.


COMMON SIGNAL INTEGRITY PROBLEMS

The problems that are most commonly experienced in nanometer technologies are related to crosstalk. The source of the problem is in the interconnect wire aspect ratios, which have more side wall capacitance compared to the self capacitance of wires in earlier technologies (Figure 1).

Figure 1 Sidewall capacitance effects increase with shrinking feature sizes.

The result is a dramatic increase in coupling capacitance (CXCOUP) between the sidewalls of adjacent tracks relative to the substrate capacitances CAREA (track base to substrate) and CFRINGE (sidewall to substrate). Furthermore, the high integration densities associated with today's devices -which can support as many as eight metalization layers -results in significant capacitive coupling between adjacent layers. This is represented by CCROSSOVER (Figure 2).


Figure 2
High integration results in significant capacitive coupling between adjacent layers.

The combination of these factors results in a tremendous increase in the complexity of crosstalk noise and timing effects.


CROSSTALK-INDUCED GLITCHES
When signals in neighboring wires transition between logic values, the coupling capacitance between the wires causes a transfer of charge. Depending on the slew of the signals (the speed of switching in terms of rise and fall times) and the amount of mutual crosstalk capacitance (CXTALK) there can be significant crosstalk-induced glitches (Figure 3).

In this example, a transition on a fast aggressor net causes a glitch to be presented to the input of the load/receiver of an adjacent victim net. This illustration presents a very simplistic view; In reality, each track may be formed from multiple segments occupying multiple levels of metalization. Thus, the resistances (R WIRE1 and R WIRE2) and capacitances (C WIRE1 and C WIRE2) will each consist of multiple elements associated with the different segments. Similarly, the mutual coupling crosstalk capacitance (CXTALK) may consist of multiple elements. Some of these will be equivalent to CXCOUP if segments of the aggressor and victim nets are neighbors on the same metalization layer, or CCROSSOVER if the aggressor and victim nets cross each other on adjacent layers (Figure 2).


Figure 3
Signals in neighboring wires transitioning between logic values can cause crosstalk-induced glitches.

The example glitch illustrated in Figure 3 represents only one of four possibilities based on the fact that a rising or falling transition on the aggressor net may be coupled with a logic 0 or logic 1 on the victim net (Figure 4).

If the ensuing low noise or high noise glitches on the victim net cross the input-switching threshold of its load/receiver, a functional (logic) error may occur. In some cases this error may manifest itself as an incorrect data value that is subsequently loaded into a register or latch. In other cases, the error may cause a latch to perform an unintended load, set, or reset.


CROSSTALK-INDUCED TIMING ERRORS
The situation becomes even more complex when simultaneous switching occurs on both the aggressor and victim nets. For example, in the case of opposing transitions, the signal on the victim net may be slowed down (Figure 5).


Figure 4
There are four possible types of crosstalk-induced glitches.

If the signal on the victim net were transitioning in isolation, it would take a certain amount of time to cross the load/receiver's switching threshold (which, for the purposes of these discussions, is assumed to be 50% of the value between a logic 0 and a logic 1). However, the glitch caused by a simultaneous transition on the aggressor net holds the victim's signal above the load/receiver's switching threshold for an additional amount of time. This can result in a downstream setup violation.

An alternative scenario occurs when a transition on the victim is complemented by a simultaneous transition on the aggressor, in which case the signal on the victim may speed up (Figure 6).


Figure 5
In this circuit, crosstalk has induced a signal delay.

In this case, the glitch caused by a simultaneous transition on the aggressor net causes the victim's signal to cross the load/receiver's switching threshold earlier than expected. This can result in a downstream hold violation.

These examples are somewhat simplistic; In a real-world design, each victim net may be affected by multiple aggressors (Figure 7).


Figure 6
Here, crosstalk has induced a signal speed up.

Conventional noise analysis tools assume single-aggressor-single-victim scenarios and lump all of the coupling capacitors together to form an inaccurate model. Accurate analysis of today's DSM designs requires each aggressor's contribution to be individually accounted for and analyzed.

Signal integrity violations can be analyzed during physical implementation in order to avoid them. However, the run time requirements of physical implementation tools are based on the design teams' goal to expeditiously implement the design so as to get early evaluation, leaving room in the schedule for refinement if necessary. Thus the analysis methods employed during implementation are intended to uncover any existing signal integrity issues using pessimistic analytical models, so as not to miss any obvious problems. By uncovering the problems early in the flow many of them are avoided during implementation.

False violation is one aspect of fast but pessimistic analysis. The other point to be taken into consideration is the completeness of the analysis. In the interest of run time the higher order physical effects are sometimes overlooked in the avoidance schemes. For example the device currents flowing through the resistive power rails cause IR drop that in turn affects the drive strengths of signals and the noise margins of the devices, which in turn affect both the timing and functionality of the design.

Figure 7 It is possible that each victim net may be affected by multiple aggressors.

A key component in the accuracy of verification is the library data. Current library characterization methodologies do not adequately address crosstalk noise and do not provide accurate data such as noise rejection curves and gate-holding resistance variation. Nor do they address voltage drop affect on delays or suitable interpolation between multi-VDD libraries used in low power designs. Conservative library data causes false errors and should be revised for accuracy. The characterization methods should be applicable to hierarchical components so that macros and IP blocks can be verified at the top level of the design.

Verification in design flows has traditionally been accomplished through expert scrutiny and tools that have become golden standards through years of validation. Spice simulation is an example of such a golden standard. However, the traditional Spice-based methods do not scale in size. Verification tools that can provide Spice accuracy as well as the run time benefits of gate-level tools will be most effective in today's design flows.

The architecture of verification tools has in the past been point-tool-centric. This causes the flow to become loaded with translators and scripts that are used to interface various point tools together, and is cumbersome and time consuming as large amounts of data need to be communicated between tools. The new direction is towards verification tools integrated with high quality components such as delay calculators, timing analyzers, parasitic extractors, crosstalk analyzers, and power grid analyzers to perform the verification task accurately and completely. The architecture allows incremental and concurrent analysis, vital to achieving the end goal. Inclusion of such verification tools in design flows will go a long way towards utilizing the full potential of nanometer silicon technology and producing competitive products.


Author Information
Dr. Rajit Chandra is vice president of technology at Magma Design Automation (www.magma-da.com).He holds a PhD in electrical engineering from London University, UK. Before joining Magma he co-founded and was senior vice president of technology of Moscape Inc, which specialized in signal integrity verification solutions. Moscape was acquired by Magma in 2000. Dr. Chandra has worked extensively in the areas of performance verification of large-scale IC designs and is actively involved in solving electrical integrity issues associated with nanometer process technology.