How far has Structured ASICs succeeded in playing the role the designer said they would play? Structured ASIC is said to be the right choice for 100,000 to 3 million units; below this range, FPGA is the right choice, and above this range, standard ASIC. While Structured ASICs may have addressed the NRE problem, a new issue that has cropped up is whether they provide the commercially viable customized SoC solutions that the end market needs.
For one thing, though Structured ASICs came into prominence only some four years ago, they have been around in some form or other for at least two decades. Despite such a long presence, they have yet to make a mark. iSuppli estimates Structured ASIC market revenue in 2004 to be merely $86 million, projected to cross $400 million in 2008, which will be a small fraction of the total semiconductor design, currently worth $22 billion. Analysts had grossly overestimated Structured ASIC market size when projecting it to grow to $300 million last year. The actual figure may be less than half of this.
Migrating to ASIC On one side Structured ASICs elicit a response signifying their end, as that from John East, President and CEO of Actel: “Structured ASIC is the last dying gasp of the ASIC business.” On the other hand, they march forward, albeit slowly and shakily, trying to create for themselves a place in the logic-device market. “This is not about who is going to win,” says Richard Wawrzyniak, Semico’s senior ASIC and SoC analyst, referring to FPGA vs Structured ASIC vs cell-based ASIC scenario. “It is about what combinations of features and functions, power, time to market, and cost best suit your needs.”
Some designers promote the idea of a Structured ASIC as an interim step towards a standard cell solution. The designer develops his concept in a Structured ASIC environment, and then migrates to ASIC as production volume ramps up. This idea does not seem to go far enough. The migration to ASIC requires the user to pay for second NRE and involves a lot of additional design work. There is a danger that the design may end up in no-man’s land—not as cheap as Structured ASIC; not as fast as standard-cell ASIC; not as flexible as FPGA. This danger must be kept in mind when using the migration path.
The chances of success when using Structured ASIC might be greater if the designer can determine the optimal number of programmable layers for customization. This will enable balancing NRE prices against routing flexibility. Fewer layers will be cheaper, but will require greater time and effort to route. Finding that “sweet spot” for NREs while providing enough number of customizable layers to deliver a seamless migration path is the key to success.
Hybrid processing approach Some designers have found that Structured ASIC technology is not necessarily faster to market than a standard cell. Though fabrication time is shorter because fewer layers are required to be programmed, in the real world where wafers wait in a line to be processed, it is not the number of layers to be programmed but the number of wafers ahead in the queue that determine final fabrication time. Some designers are addressing this issue through a “hybrid processing approach,” wherein designers have full control over scheduling, and can typically deliver prototypes 10 to 14 days after tape out—a speed unapproachable in a standard cell.
Some doubts have been expressed that Structured ASIC technology really leads to any cost saving. This platform can save mask NRE costs and time to market; however, these savings are more than offset by a greater front-end cost of the design and development phase, and a greater design risk. To avoid the cost of extra chip spins, the user has to make huge investment in physical verification tools that are becoming more costly into deep nanometrics.
Whatever be the value proposition of Structured ASICs, they are neither going far nor going away.
