The IEEE has recently approved the SystemVerilog hardware-description and -verification language as IEEE Standard1800-2005. EDA-tool users in India, particularly those providing design services to clients, see the ratification of this standard as a significant development. “SystemVerilog will help speed up verification of multimillion-gate designs,” says GH Rao, vice president of R&D and technology services at HCL Technologies Ltd. “It will also improve the development time of IP [intellectual-property]-based designs, such as SOCs [systems on chips]. We plan to use SystemVerilog from Cadence for verification by the second half of 2006.” Rao says that SOC design for multimedia and telecom applications needs standardization of system-level simulation and approval.
“The SystemVerilog standard will provide a great boost to our operations,” says Ravi Amur, assistant vice president at the business unit of Hitec at Satyam Computer Services Ltd. SystemVerilog expands language-based electronic design with new and powerful design and verification capabilities based on the Verilog-2005 IEEE Standard1364-2005. Its enhancements include the extension of memory-system tasks for complex memory modeling, operator overloading for simplified expressions, and tagged unions with pattern matching for code conciseness and improved formal analysis.
The main benefits EDA users see from the new standard include improved interoperability between EDA tools from different vendors and unification of methodology for design and verification. Although agreeing with Rao on the design-productivity benefits of SystemVerilog, SN Padmanabhan, vice president of R&D services at MindTree Consulting, cautions, “The design and verification teams will have to learn a newer language and methodology if they want to leverage its full potential.” He feels that standardization by itself will guarantee acceptance as a sign-off tool. “Only after many designs [over technology nodes such as 180, 130, 90, and 65nm] are proved will clients be confident about using this product as a sign-off tool,” he says.
