Inexpensive envelope tracker handles wide signal variations

Converting band-limited NRZ (non-return-to-zero) data to a digital format suitable for microprocessors and other digital systems poses problems when a signal’s duty cycle or amplitude varies or when its average level unpredictably wanders within a given dc range. Transferring the signal to a fixed-reference comparator using ac coupling produces poor results because changes in duty cycle cause variations in average signal level that result in jitter or distortion of the output signal’s timing.

Based on diodes and RC networks, an envelope tracker creates a voltage between the input signal’s excursions (Reference 1). Using the midpoint voltage as a reference, the comparator generates a digital output signal that faithfully replicates the original signal’s timing information. Although highly effective for relatively large signals, a diodebased circuit can introduce errors or even fail completely for inputs that are small relative to a diode forward-voltage drop or when the input’s average level drifts toward either of the circuit’s supply-voltage rails.

Requiring no diodes, the single-supply circuit in Figure 1 reconstructs a band-limited NRZ data stream whose duty cycle can vary from less than 5% to more than 95% and whose amplitude varies from less than 100 mV to the supply-rail voltage—5V, for example. Furthermore, the circuit tolerates an average signal level that falls between the two supply rails. The circuit comprises triple analog switch I₁, dual comparator IC₂, and a few passive components.
<%@ LANGUAGE="VBSCRIPT" %>
<% Randomize: ord=int(rnd*1000000000) %>


VUC and VLC, on capacitors C3 and C4. Two equal-valued resistors, R4 and R5, between C3 and C4, produce a third voltage, VMID, that’s equivalent to the input signal’s midlevel voltage, VM. Capacitor C2 smoothes and filters VMID, which serves as a reference potential for output comparator IC2B. R2, R3, and ₁ provide temporal hysteresis, ensuring clean switching of VOUT, even for relatively small inputs.

sTo understand the circuit’s operation, assume that C₄, C₂, and C₃ all discharge; that is, V_LC, V_MID, and V_UC are all 0V. Because input signal V_IN is greater than VMID and the potential at IC2A’s inverting input, both comparators’ outputs go high and cause the three analog switches to assume the positions in Figure 1. Now, assume that V_IN is at its positive peak amplitude, V_U. Capacitor C₃ now charges through R₁ and the on-resistances of the three switches. Provided that C₃ is not too large, VUC rapidly acquires a value roughly equal to VU.

When V_IN falls below VUC, comparator IC_2A’s output goes low and forces analog switch I_1C to change state and disconnect C₃ from V_IN. Ignoring comparator input-bias currents and assuming negligible switch-leakage currents, C₃ can now discharge only through R4. If R₄ is large enough, the relatively slow discharge rate allows VUC to remain roughly equal to V_U.



During C₃’s charging interval, C₂ also charges through R₄. Depending on the values of C₂ and R₄ and on the duration of the input signal’s positive-going pulse, voltage VMID may exceed the input signal’s lower level, V_L. If VMID exceeds VL, comparator IC2B trips when V_IN approaches VL, and the resulting low level at VOUT causes both I_1A and I_1B to change state. Capacitor C₄ now connects to V_IN through R1 and the switches’ on-resistances and quickly charges to a level at which V_LC approximately equals V_L.

Depending on component values and on the input signal’s timing parameters, several cycles may elapse before the circuit’s voltage levels stabilize at their quiescent values, at which V_UC≈V_U, V_LC≈V_L, and V_MID≈V_M. However, careful selection of components ensures that the circuit rapidly reaches equilibrium. Ensuring that the comparator trips properly when V_IN goes below V_U or above V_L requires that R₁ provide a minimum amount of impedance of 100Ω to 1kΩ between V_IN and IC_2A’s inverting input. Higher values result in sluggish charging of C4 and C3. In many designs, the combined on-resistances of I_1B and I₁C may allow omission of R₁.



The presence of I_1B, I_1C, and IC_2A ensures that C₃ can charge when V_IN is close or equal to VU and that C₄ can charge only when V_IN is close or equal to V_L. Without I₁B, I_1C, and IC_2A—that is, with V_IN connected directly to R₁—C₃ would discharge on the downward slope of V_IN between V_U and V_M and would thus pull down V_UC. Similarly, C₄ would continue to charge on the upward slope of V_IN between V_L and V_M and would thus pull up V_LC. Although VMID might be roughly equal to V_M, such a minimal configuration performs relatively poorly, particularly for small signals and at extreme duty cycles.

The components in Figure 1 produce good results for input frequencies of 5 to 50kHz. Frequencies lower than 5kHz may require larger capacitor values, and operation higher than 50kHz may require reduction of capacitors’ values and selection of a comparator with minimal response time. With properly selected components, the circuit performs well at baud rates to or exceeding 128kbps.

The values of R₅, R₄, C₂, and, to a lesser extent, the analog switches’ on-resistance and R₁, C₄, and C₃ determine the circuit’s response time to a sudden change in input signal amplitude or average level. Making C₂ approximately 10 times smaller than C₄ and C₃ ensures a rapid “attackâ€� time, but too small a value can result in excessive ripple and noise on V_MID. For reliable operation, use equal values of close-tolerance resistors of 100kΩ to 1MΩ for R₄ and R₅. If you use high-value resistors for R₄ and R₅, choose a comparator with low input-bias currents for IC₂. For detection of signals that might approach the positive-supply rail, the 0V rail, or both, make sure that IC₂ offers rail-to-rail input capability. Bypass each IC’s power supply connections with low impedance ceramic capacitors.

Note that, with no input signal present (that is, when applying a dc level to V_IN) VOUT may contain random pulses caused by noise and the comparators’ attempts at maintaining VMID equal to V_IN’s average dc level. To eliminate the pulses, remove ₁ to replace temporal hysteresis with “normalâ€� hysteresis, but ensure that the hysteresis levels that R2 and R3 set are not excessively large relative to the minimum input-signal amplitude.

Figure 2 shows the circuit’s response to a bandwidth-limited input signal of approximately 5% duty cycle and 75mV amplitude. The horizontal trace, V_MID, neatly bisects the waveform. The bottom trace shows the reconstructed signal at VOUT. In Figure 3, the circuit processes the real-world output of an inductively coupled transceiver (upper trace) of approximately 200mVp-p. Again, the lower trace shows the reconstructed signal at V_OUT.


REFERENCE
1. Whipple, Roger C, “Envelope tracker quells jitter,� EDN, July 7, 1994, pg 102, www.edn.com/archives/ 1994/070794/14di8.htm.