Hartley oscillator requires no coupled inductors

Examine a traditional Hartley-oscillator circuit, and you’ll note its trademark: a tapped inductor that determines the frequency of oscillation and provides oscillation-sustaining feedback. Although you can easily calculate the total inductance for a given frequency, finding the coupling coefficient, k, may require experimental, or “cut-and-try,� optimization. This Design Idea presents an alternative equivalent circuit that allows you to model the circuit before building the prototype.

Figures 1a and 1b show the Hartley oscillator’s equivalent tuned circuit, the equations that calculate its components, and component values for an 18MHz oscillator. The mutual inductance is For the equivalent circuit, the equations are: L_A=–L_M, L_B=L₂–L_A=L₂+L_M, and L_C=L₁–L_A=
L₁+L_M. The rest of the equations for the equivalent circuit are:





and



Unfortunately, a truly equivalent circuit requires a negative inductance, LA. However, for frequencies near the resonant frequency, f₀, you can replace the negative inductor with a capacitor, in which C_A replaces L_A (Figure 1c). Note that the equivalent circuit’s derivation neglects parasitic winding resistances and capacitances.
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Figure 2 illustrates an oscillator and output buffer using the equivalent circuit. The constructed circuit generally performs as you would expect from an initial Spice simulation. During testing, several components’ values required tweaking, and multiple iterations of Spice analysis ultimately yielded the final design. The oscillator’s tank circuit comprises LB, LC, C4, and C5, plus capacitance provided by voltage divider C6, C7, and C8. This capacitance of approximately 6pF includes Q1’s and Q2’s input capacitances and some stray capacitance. The total tank capacitance of 66pF approximates the calculated value of 67pF. Capacitors that connect to the tuned circuit feature ceramic-dielectric construction with NP0 temperature coefficients.



Inductors L_B and L_C comprise air-core coils with their axes at right angles to each other to minimize stray coupling. However, vibration affects their inductances, and, in a final design, both should comprise windings on dielectric or toroidal cores, providing that the toroids’ temperature coefficients of inductance are acceptable for the intended application. Reference 1 provides basic designs for both inductors, and adjusting the spacing of their turns tunes the oscillator to exactly 18MHz. For a more rigorous design, you can measure the inductors before installation, but parasitic effects may require readjusting the inductors’ values.

The capacitive voltage divider comprising C₆, C₇, and C₈ applies the proper signal levels to Q₁ and Q₂. Because the divider “seesâ€� the tank circuit’s effective capacitance as only 6pF, the remaining 60pF can comprise a variable capacitor if the design calls for a tunable oscillator. In this example, the output stage comprising Q3 and its associated components would require modification to provide more bandwidth if the oscillator requires a tuning range exceeding ±2MHz.

Capacitor C₃ bootstraps Q₁’s Gate 2 to Q₁’s source to provide additional gain from Q₁ and to reduce its Gate 1 input capacitance below its value of approximately 2.1pF (Reference 2). An 8.3μH inductor, L₂, connects to Q₁’s source and presents relatively high impedance at 18MHz and provides a dc path from Q₁’s source to ground through R₃. The impedance of L₂ at 18MHz comprises an inductive reactance of about 940Ω in parallel with a resistance of approximately 3.5kΩ, which results in a choke with low resistive losses. You can substitute a smaller inductor for L₂ provided that its inductance and reactance approximate the original’s values. You can use a standard-value 8.2μH choke for L2 provided that its resistive losses meet these low-loss criteria and that its inherent series resistance is 2Ω or lower to avoid upsetting Q₁’s dc bias voltage. The inductance and resonance of the choke for L1 are less critical than those for L2, but using a choke with low resistive losses at L1 helps avoid spurious resonances.

Source follower Q₂ drives the output stage, which uses a pin matching network to transform the 50Ω output load to 285Ω at Q₃’s collector. Bootstrapping Q₂’s Gate 2 by one-half of its output voltage increases the source follower’s gain and dynamic range and reduces its input capacitance. Potentiometer R5 adjusts the circuit’s output level from about 0.9V p-p to approximately 1.5V p-p across a 50Ω load. The circuit’s frequency remains stable at a constant room temperature of about 23°C. Also, the output level- control circuit remains stable even if you apply no load to the output. For a fixed-frequency oscillator, the output circuit’s loaded resistive losses of approximately 4 provide adequate bandwidth without retuning L₃, C₁₆, and C₁₇.



To set the output level to a safe maximum, connect a 50Ω load to the output and adjust the output to 1.5V p-p. The drain-to-source voltage you apply to Q1 remains at a safe level for all loads from 50Ω to no load, even though the output voltage level increases as the load resistance increases. To avoid exceeding Q1’s specified maximum 12V drain-to-source voltage, do not exceed an output-voltage setting of 1.5V into a 50Ω load. Note that zener diode D1 reduces Q1’s drain voltage to provide an additional safety margin.

In a previous Design Idea, an operational amplifier and a dioderectifier circuit control the oscillator’s gain by applying a variable voltage to Q1’s Gate 2 (Reference 3).

In this design, a simple passive circuit serves the same purpose. A portion of the signal at Q3’s collector drives a voltage doubler comprising D2, D3, C20, and C21. The voltage doubler develops a negative voltage, part of which drives the junction of R18 and C19, the control voltage node. This control voltage node also receives a positive voltage through R17 from variable resistor R15, and the resultant voltage sets the output-signal level. At start-up, only a positive voltage is present at Q1’s Gate 2, and Q1’s maximum gain easily starts the oscillator.

When the output reaches steady state, the control voltage decreases and maintains oscillation at a signal level that the output-level control determines.


REFERENCES
1. Reed, Dana G, Editor, “Calculating Practical Inductors,� ARRL Handbook for Radio Communications, 82nd Edition, American Radio Relay League, 2005, pg 4.32.

2. “Practical FET Cascode Circuits,� “Designing with Field-Effect Transistors,� pg 79, Siliconix, 1981.

3. McLucas, Jim, “Stable, 18-MHz oscillator features automatic level control, cleansine-
wave output,� EDN, June 23, 2005, pg 82, www.edn.com/article/CA608156.