Reducing congestion in ICs by stacking chip layers is not a new idea. It has been around for at least three decades. However, the idea is catching on fast now as traditional scaling routines of shrinking transistor dimensions to achieve higher performance do not work. It is not cost alone that's challenging Moore's Law. The chips have become so congested that if designers continue to cram more transistors into a smaller flat chip, they will not be able to create better performance in chips at the same pace as postulated by Moore's Law that has worked well for over 40 years.
3D: THE LATEST CHOICE ICs have traditionally been twodimensional. Leveraging the third dimension in product design and manufacturing to create a 3D chip is emerging as the latest choice to keep Moore's Law alive. Not all agree on a common definition of a 3D chip. Some designers say the 3D chip comprises multiple layers of semiconductor devices within a monolithic chip. Others say that employing techniques that bond multiple dice together, almost like a multi-chip package connected at the wafer level, leads to 3D chips. Yet others call optimization of single-layer designs 3D because the layer of devices incorporates 3D shapes for better packing density. I think the definition of 3D IC is veering around to having just one base layer of silicon with active wafers layered on top with all the processing done at the wafer level that makes the chip monolithic. The wafers can be connected anywhere with short interconnects only a few microns long.
Designers are working on combining memory with processors. This will drastically reduce memory access time, especially useful for weather forecasting or calculations related to nuclear plants. 3D chips can offer this combination. Such chips can go beyond normal chips to create a whole range of new functionalities. For instance, integrating biochips with silicon chips can open up vast application areas in medical science.
3D chips are currently at a stage ranging from productionization to early adoption. The US and Japan are in the lead, with American companies Ziptronix and Tezzaron Semiconductor, among others, offering products. The Japanese startup Zycube is centering on image processing. Early 3D devices have already hit the market, particularly in synergistic combinations such as processor-plus-memory. Sales have been low.
I think for all these years academic institutions rather than the industry were interested in 3D chips. But now with major vendors such as IBM, Infineon, and Toshiba reporting to be developing 3D technology and designing 3D products, 3D electronics should see faster growth and eventually come into its own.
3D MARKET SIZE iSuppli estimates that the market for 3D devices was $10 million in 2005. The potential is extremely high. Probably the entire core silicon (ASICs, ASSPs, PLDs) market, as well as some of the memory, microprocessor, and microcontroller markets, will change over to 3D. Leading the way should be microprocessors, which incorporate both logic and memory in a single package. Flash-based microcontrollers and advanced AASPs and ASICs are other applications that would contribute much to maturing of the 3D devices industry. iSuppli has offered a highside forecast of $3.3 billion for 3D chips in 2010, growing rapidly to $17.3 billion in 2015.
I think achieving these figures will depend more upon cost issues than technology issues. On the technology front, the key to 3D devices is productionization and scalability to future process nodes without limiting the die size. Designers will get over these problems, but more important for them is to enable designs that make 3D-device manufacturing costcompetitive with 2D products. The IT industry has become used to getting higher and higher performance, but at lower costs.
