Integrating boundary scan into multi-GHz I/O circuitry

The external interfaces of integrated circuits (ICs) have been experiencing two trends: significantly improved testability due to IEEE standards under the 1149 umbrella, and significantly increased performance requirements as system speeds and bandwidths grow. Unfortunately in very high speed interfaces such as SerDes (serializer/deserializer) channels operating in the GHz range, boundary scan techniques embodied in both IEEE Std 1149.1[1] and Std 1149.6[2], can degrade the mission performance of such high speed I/Os. Fortunately, creative application of the 1149 standards allows both performance and testability goals to be achieved.

BOUNDARY SCAN
The principle behind boundary scan testing of a PCB is to add test circuitry internal to the ICs, and to use that circuitry to exercise the interconnections between ICs. IEEE Std 1149.1 specifies that scan-based control and observe points be added to the I/O pins of the ICs, that these scan registers be connected to form a boundary scan chain, and that this scan chain be accessed via a test access port (TAP) with a standard set of instructions, thus enabling chip-tochip interconnect testing without direct physical access to the pins of a chip. Figures 1a and 1b show a simplified view of a bidirectional I/O pin before (a) and after (b) the addition of 1149.1 boundary scan. With the added circuitry, this I/O is now able to:
• Drive either digital value to the pin from the boundary register labeled DR BSR (the EXTEST instruction),
• Tristate the pin via the boundary labeled TS BSR, and
• Sample the value received from the pin in the boundary register labeled RX BSR.

Two of the shortcomings of IEEE Std 1149.1, its inability to handle ac-coupled nets, and its poor detection of faults on differential nets, are addressed by IEEE Std 1149.6, which adds circuitry for edge-based testing of ac-coupled nets as well as dual single-ended treatment of differential receivers. Figure 2 shows a simplified view of a differential channel before (a) and after (b) the addition of 1149.6 boundary scan. Section 6.2 of IEEE Std 1149.6 specifies the use of dedicated test receivers ("testrx" in Figure 2b) with hysteretic comparators prior to the boundary scan registers; these allow reconstruction of the driven waveform on ac-coupled nets.
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With the added circuitry in Figure 2b, the ends of this channel are now able to:
• Drive either pulse polarity to the TX pins from the boundary register labeled "TX BSR" (the EXTEST_PULSE instruction),
• Drive a series of pulses to the TX pins from the boundary register labeled "TX BSR" (the EXTEST_TRAIN instruction), and
• Capture the direction of the last edge (rising or falling) received from the RX pins in the boundary registers labeled RX+ BSR and RX- BSR.

HIGH SPEED I/O
It is becoming increasingly common for ICs to employ highspeed serial links running at GHz frequencies with embedded clocking to carry data. These data streams are created by parallelto- serial conversion on the transmitting IC, and resolved by serial-to-parallel conversion on the receiving IC. Figure 3 shows a highly simplified view of the parallel-to-serial conversion on the transmit side. Note the implicit clock domain crossing in the parallel-to-serial converter: the left side of Figure 3 is running in the 1X_CK domain, while the serial shift register inside the parallel-to-serial converter runs at 10 times the frequency (in the 10X_CK domain).

The addition of the boundary scan hardware to a chip pin, as shown in Figure 1, will affect the performance of the original circuit due to additional multiplexer delay in series with the driver data, the tristate control, and the additional fanout and load on the receiver. For example, at the common 3.125GHz data rate the delay through the added multiplexer could consume a substantial portion of the 320ps period, and the additional logic can only increase jitter.

DRIVER-SIDE BOUNDARY SCAN INSERTION IN THE PARALLEL DOMAIN
The placement of the output boundary scan register just in front of the driver is not mandated by IEEE Std 1149.1, which permits an arbitrary analog circuit between the boundary register and the pin (see Figure 10-7 of IEEE Std 1149.1- 2001). Though the parallel-to-serial converter is largely digital, it can be treated as an encapsulated analog circuit for the purposes of applying the standard, resulting in placing the boundary scan register in the parallel domain (Figure 4).

In Figure 4 the single value in the boundary scan register is copied to all of the parallel inputs, then serialized and presented as a high-speed stream of constant values. This high-speed stream is indistinguishable from dc, and thus satisfies the requirements of boundary scan.

This boundary scan register placement requires the parallel-toserial converter to be operational during boundary scan testing, which implies that the clocks used in that portion of the circuit must be running. This may appear to be a violation of the intent of IEEE Std 1149.1, since there should be no functional dependencies on the chip to perform an EXTEST operation. However, many types of I/O circuits require preconditioning before they will operate, and it is not uncommon to include a "design warning" section in the BSDL that spells out the preconditions for performing boundary scan, which, in this case, includes the recipe for providing the appropriate clocking. Most parallel-to-serial converter circuits employ a phase-locked loop (PLL) to generate the high speed clocks. A free-running oscillator could be used as the source of the PLL reference clock during boundary scan test because the considerably relaxed data required for boundary scan are frequencyand phase-independent. Thus, the "analog circuit" can include an autonomous clock generator.

The placement of the boundary registers in the parallel domain requires that a considerable amount of circuitry be operational in order to perform the simplest boundary scan test. This is not a violation of the standard or a weakness of this approach since a successful boundary scan test not only demonstrates that the interconnect is functional but that a sizeable portion of the IC is as well. Assuming that the IC was fully tested at the component level and has not suffered an early life failure, a failing boundary scan test can still be diagnosed as an interconnect problem—with a marginal increase in the probability that the IC may be suspect.

Finally, the modifications specified by IEEE Std 1149.6 for edge generation are exactly the same as they would be were the boundary register placed in the serial domain.

RECEIVER-SIDE BOUNDARY SCAN INSERTION VIA IEEE STD 1149.6
Integrating boundary scan on the receiver side of a high speed link is simpler than for the driver side. One of the key operations performed on an incoming data stream by a receiver is clock recovery. With the constant dc values present during boundary scan testing, there is no clock to recover, so it is not necessary to place the receiver-side boundary scan registers in the parallel domain; in fact, for differential channels it is not even desirable.

Receiver-side boundary scan for advanced I/Os has been thoroughly examined and specified in IEEE Std 1149.6, which details the design of a test receiver capable of both edge detection for ac-coupled nets and level detection for traditional dc-coupled nets. These test receivers are placed in parallel with the mission receivers, and are thus in the serial domain for the types of I/Os described here.

SILICON IMPLEMENTATION AND RESULTS
The complete boundary scan implementation shown in Figure 5 was implemented in a 0.13μm, 1.2V test chip with several differential transmit/receive pairs[3]. The nodes labeled as TX+, TX-, RX+, and RX- represent the test points measured. The boundary scan test results for level-based dc EXTEST are shown in Table 1, and the results for edge-based EXTEST_ PULSE in Table 2. The "VV" notation in Table 1 indicates that the initialized value (V) in the test receiver was not changed during EXTEST when the driver was ac coupled to the receiver; this is exactly the expected behavior, because the coupling capacitor blocks the dc level.

The tests verified the correctness of all boundary scan operations and showed that the mission performance of the serial links was unaffected by the addition of the boundary scan circuitry.

Jitter introduction on the driver side is by definition zero, since the serialized data goes through a retiming process in the 10X_CK domain. As long as the additional multiplexer delay associated with the boundary scan cell in the parallel domain is accounted for in static timing analysis, there will be no impact on the functional performance of the transmitter. The high input impedance of the test receivers added a negligible additional load beyond the mission receivers.

CONCLUSION
This paper has demonstrated a viable circuit design for both the driver and receiver portions of boundary scan for GHz-speed I/Os. The key innovations were the placement of the driver-side boundary scan register in the parallel domain, and the use of 1149.6 test receivers in the serial domain, which achieved correct implementation of boundary scan, with negligible impact on the mission mode operation of the high-speed serializer/deserializer circuitry.

Reference

1. IEEE Std 1149.1-2001, "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE, USA, 2001.

2. IEEE Std 1149.6-2003, "IEEE Standard for Boundary- Scan Testing of Advanced Digital Networks," IEEE, USA, 2003.

3. Vandivier, Wahl, and Rearick, "First IC Validation of IEEE Std 1149.6", Proc. International Test Conference, 2003, pp. 632-639