Mears reduces gate leakage for deep sub-micron processes

Mears Technologies has been launched to re-engineer the physical properties of silicon in order to reduce gate leakage by as much as 70 percent in NMOS transistors, and up to 90 percent in PMOS transistors, while maintaining drive current for a variety of deep sub-micron processes. Through this approach, Mears intends to enable semiconductor companies to continue with their aggressive device roadmaps while still leveraging the semiconductor industry’s existing manufacturing infrastructure.

Mears is tackling the issues of chip performance and power consumption head-on with its new MST Platform. Static power dissipation, also called gate leakage, can account for as much as 70 percent of the total power budget of devices manufactured at the 65 nm process node. Using a band engineering approach, Mears has developed its patented MST Platform to reduce gate leakage, providing a advantage for all applications that benefit from reduced power consumption. In addition, the new technology will enhance drive current, which relates directly to increased semiconductor speed.

Robert J. Mears, founder and president of Mears Technologies, said, “The explosive growth of cell phones and other personal electronics devices has created conflicting demands for semiconductors with increased performance and reduced power consumption. The ability of the industry to respond to these demands continues to depend on the electrical properties of a single material–silicon. As chipmakers attempt to squeeze more performance out of their transistors, the fundamental properties of silicon and its native oxide have become the limiting factor. And while some approaches have been successful in addressing performance requirements, power issues continue to exist. Through a new approach to silicon engineering, we are able to alter the properties of the silicon to improve the power efficiency and speed of transistors manufactured using deep sub-micron process nodes such as 65 nm, 45 nm and beyond, while maintaining compatibility with standard CMOS manufacturing equipment that is used for the vast majority of today’s semiconductors.�

Mears’s MST Platform is designed to be fully compatible with semiconductor manufacturers’ baseline processes, whether it be bulk CMOS, strained silicon or silicon-on-insulator. The power improvements are achieved through a band engineering approach that is based on a deep understanding of the quantum mechanics of modern deep-submicron devices. In its first implementation, MST Generation 1 is a channel replacement technology incorporating a silicon laminate, or superlattice layer, which requires no new materials be used in the fabrication process. This silicon-on-silicon solution adds only a few steps to the standard CMOS manufacturing flow—and at virtually no additional cost or impact to production yields.

Mears Technologies