Wafer-level Packaging Pushes Past New Mobile Demands 25/8/2010

We hear a lot these days about 3D integration and the many benefits that vertical scaling can bring with it. But there is a significant amount of semiconductor packaging innovation still taking place in the 2D arena as prominent consumer applications put more demands on chip size, performance, functionality, and cost. And ultimately, those 2D innovations will also lead to further enablement of 3D technologies. As traditional CMOS scaling finally reaches its limits, the industry is looking at a variety of ways to continue on a path of functional ...

IMEC Touts SiGe MEMS and GaN-on-silicon Technologies 23/8/2010